Functional Validation of Mixed Hardware/Software Systems based on Specification, Partitioning, and Simulation of Test Cases

Tecs is a test case development methodology for the functional validation of large electronic systems, typically consisting of several custom hardware and software components. The methodology determines a hierarchical top-down test case development process including test case specification, validation, partitioning and implementation. The test case development process addresses the functional validation of the system and its components such as ASICs, boards, HW and software modules; it does not facilitate timing or performance verification. The system functions are used to define test cases at the system level and to derive sub-functions for the system components. Test cases are specified, using a special purpose formalism, and validated before they are applied to the system under test. Furthermore, we propose a technique to partition test cases corresponding to the partitioning of the system into sub-systems and components. This technique can significantly reduce system simulation time because it allows the full validation of system functions by simulation at the sub-system and component level. The system model need only be simulated with a reduced set of stimuli to validate the interfaces between sub-systems. We present a test case specification language and tools that support the proposed methodology. The validation of a switching function illustrates methodology, language, and tools.     

An FPGA Design for Real-Time Image Denoising

The increasing use of images in miscellaneous applications such as medical image analysis and visual quality inspection has led to growing interest in image processing. However, images are often contaminated with noise which may corrupt any of the following image processing steps. Therefore, noise filtering is often a necessary preprocessing step for the most image processing applications. Thus, in this paper an optimized field-programmable gate array (FPGA) design is proposed to implement the adaptive vector directional distance filter (AVDDF) in hardware/software (HW/SW) codesign context for removing noise from the images in real-time. For that, the high-level synthesis (HLS) flow is used through the Xilinx Vivado HLS tool to reduce the design complexity of the HW part. The SW part is developed based on C/C++ programming language and executed on an advanced reduced instruction set computer (RISC) machines (ARM) Cortex-A53 processor. The communication between the SW and HW parts is achieved using the advanced extensible Interface stream (AXI-stream) interface to increase the data bandwidth. The experiment results on the Xilinx ZCU102 FPGA board show an improvement in processing time of the AVDDF filter by 98% for the HW/SW implementation relative to the SW implementation. This result is given for the same quality of image between the HW/SW and SW implementations in terms of the normalized color difference (NCD) and the peak signal to noise ratio (PSNR).     

FPGA implementation of a HW/SW platform for multimedia embedded systems

This paper presents a HW/SW platform for embedded video system. It has been designed around an embedded RISC processor and FPGA technologies and provides video input and output interfaces. The configurable platform has been used to implement a real time video processing and vision systems. The Altera’s Nios II development board was chosen to realise this real time video platform which uses μClinux as embedded Linux Operating System. Experimental results using H.263 video encoder show that this platform provides enough resources and speed to implement even complex multimedia embedded systems in real time.     

Virtual Prototyping For Modular And Flexible Hardware-Software Systems

The goal of this work is to develop a methodology for fast prototyping of highly modular and flexible electronic systems including both, software and hardware. The main contribution of this work is the ability to handle a wide range of architectures. We assume that hardware/software partitioning is already made. This stage of the codesign process starts with a virtual prototype, an heterogeneous architecture composed of a set of distributed modules, represented in VHDL for hardware elements and in C for software elements, communicating through communication modules. This work concentrates on a modelling strategy that allow virtual prototype to be used for both cosynthesis (mapping hardware and software modules onto an architectural platform) and cosimulation (that is the joint simulation of hardware and software components) into an unified environment. The main contribution is the use of a multi-view library concept in order to hide specific hardware/software implementation details and communication schemes. In particular this approach addresses the problem of communication between the hardware and software modules.     

Automatic VHDL-C Interface Generation for Distributed Cosimulation: Application to Large Design Examples

For functional validation of heterogeneous embedded systems, hardware/software (Hw/Sw) cosimulation methodology is mandatory. This paper deals with a distributed cosimulation environment for heterogeneous systems prototyping. The cosimulation environment allows handling all kinds of distributed architectures regardless the communication scheme used, cosimulation at different levels of abstraction and smooth transition to the cosynthesis process. The approach can handle any number of hardware modules, software modules, and debugging tools, which can be used simultaneously. This flexibility is obtained thanks to an automatic cosimulation interface generation tool, which creates links between Hw and Sw simulation environments. The resulting environment is very easy to use and our cosimulation model has been validated on very large industrial examples. The experiments show that VHDL-C cosimulation is faster than classical simulation approaches.     

Participatory game prototyping – balancing domain content and playability in a serious game design for the energy transition

Abstract

Communication designers have historically been accused of neglecting end-user perspectives, believing designers are experts at creating inspired designs. Codesign has been applied to many design fields, however developing methods for engaging end-users have had little traction in communication design practice. In an era of end-user engagement, communication designers are left wondering how and when to include end-users in the design process and if codesign offers any benefits to project outcomes. This study trialled codesign workshops across two communication design case studies. Both studies involved non-profit contexts where designers and staff co-created communication design strategies, one for sustainable cleaning in childcare centres and the other for asthma management and awareness. The findings reveal that structured, hands-on generative toolkits conducted in small groups, sparked conversation and prompted innovative ideas whereas evaluating ideas with ranking toolkits blocked dialogue and hindered idea progression. Evaluation tooolkits based on ranking ideas created unexpected barriers to engagement, as end-users disengaged from the codesign process. I argue codesign can benefit communication design when structured hands-on generative toolkits simulate a perceived familiar environment, creating a conversational forum for ideas to flow while participants enjoy creating things with their hands.     

Care towards posttraumatic growth in the era of digital economy

ABSTRACT

This article offers a reflection on how we might co-design with and for care amid the era of digital economy through a critique of current approaches to supporting mental well-being outside of therapy. Lenses of care theory and posttraumatic growth guide this critique, examining six themes of creative approaches that have been identified through a thematic review of 83 existing interventions: online communities, digitisation and re-design of psychology intervention, biometrics and data-driven, creative sharing of stories, symbolic engagements, and creative offerings of comfort and encouragements of self-care. In particular, approaches that lie within the sharing economy are scrutinised, presenting neoliberal drives that oppose its values of fairness and equity. Involvement of trusted others in the co-design of care entanglements is proposed, suggesting that these involvements would allow for reciprocal care encounters to be personalised towards those who have experienced trauma and their trusted others.     

纯滞后对象的鲁棒状态优化设计方法

纯滞后对象是一种很难控制的对象。针对纯滞后对象,提出一种串级双环状态反馈控制方式,使这种对象获得较理想的控制品质。系统的设计方法包括：采用数值逼近方法将对象拟合成有理多项式,并选择一种近乎理想的最优低通滤波器作为串级系统内外环的参考模型,并引入状态观测器,大幅度地减少状态的检测数量;采用内外环系统的协调设计,拉开内外环回路的操作频率;同时引入伺服补偿器,大大提高系统的鲁棒性。通过具体的工业对象进行仿真实验,证实该方法相当有效。     

基于状态反馈的纯滞后系统的优化设计方法

纯滞后对象是一种很难控制的对象。本文针对纯滞后对象，提出一种串级双环状态反馈控制方式，使这种对象获得较理想的控制品质。系统的设计方法包括：采用数值逼近方法将对象拟合成有理多项式，并选择一种近乎理想的最优低通滤波器作为串级系统内外环的参考模型；根据串级内、外环不同结构分别采用开环和闭环校正，并引入状态观测器，大幅度地减少状态的检测数量；同时采用内外环系统的协调设计，拉开内外环回路的操作频率，有利于提高系统的鲁棒性。本文通过两个工业过程中的纯滞后对象进行仿真实验，证实本文方法相当有效。     

Interlanguage Communication Synthesis for Heterogeneous Specifications

Nowadays the design of complex systems requires the cooperation of several teams belonging to different cultures and using different languages. It is necessary to dispose of new design and verification methods to handle multilanguage approaches. This paper presents an approach for the interlanguage communication synthesis of heterogeneous specifications. The system is represented by a set of interconnected subsystems specified in different languages with different concepts, different interface types, different communication schemes and some of them can even be IP modules. The subsystems exchange data through abstract communication channels. The objective is to refine the abstract communication channels into an implementation. The result is a set of interconnected processors communicating through signals, buses and dedicated components. An example illustrates the usefulness of this approach for the design of an adaptive speed control system that was described in SDL and Matlab.