The HybridUML profile for UML 2.0

In this article, a new UML extension for the specification of hybrid systems, where observables may consist of both discrete and time-continuous parameters, is presented. Whereas hybrid modeling constructs are not available in standard UML, several specification formalisms for this type of system have been elaborated and discussed, among them the CHARON language of Alur et al. which possesses already several attractive features for modeling embedded real-time systems with hybrid characteristics. Adopting this as a basis, the profile inherits formal semantics based on CHARON, so it offers the possibility for formal reasoning about hybrid UML specifications. Conversely, the CHARON framework is associated with a new syntactic representation within the UML 2.0 world, allowing to develop hybrid specifications with arbitrary CASE tools supporting UML 2.0 and its profiling mechanism. The “look-and-feel” of the profile is illustrated by means of a case study of an embedded system controlling the cabin illumination in an aircraft. The benefits and weaknesses of the constructed hybrid UML profile are discussed, resulting in feed-back for the improvement of both UML 2.0 and the CHARON formalism. The work presented in this article has been investigated by the authors in the context of the HYBRIS (Efficient Specification of Hybrid Systems) project supported by the Deutsche Forschungsgemeinschaft DFG as part of the priority programme on Software Specification - Integration of Software Specification Techniques for Applications in Engineering.     

基于UML-RT的复杂嵌入式系统建模方法及其应用

分析了UML在实时系统设计中的优点和需要解决的主要问题,论述了基于UML RT的实时嵌入式系统设计方法,并且对其进行扩展以支持数据流计算模型的建模,最后以汽车巡航系统为例加以说明。     

On a time enriched OCL liveness template

It is increasingly recognised that non-functional requirements should be considered at the earliest stages of system development. Unified modelling language (UML), as a standard, should therefore include notation to capture such requirements. Among these, timing has received considerable attention by the modelling community with several timed extensions of UML diagrams, a UML profile and tools. However, timing constraints are, generally, not captured in a satisfactory way during design. We propose to use UML's object constraint language (OCL) for this purpose, and provide a simple time enriched liveness template for OCL. We describe the benefits of using this template. Having verification in mind, several logic-based formalisms could be chosen to underly OCL. We consider a novel real-time logic of knowledge, and argue why logics of knowledge are useful and promising in this context. We illustrate our approach with a distributed real-time system. Future work and further benefits of the knowledge-based framework are discussed at the end of the paper. Work reported here was supported by the EPSRC grants GR/R16891 and GR/N13999.     

A prototyping language for real-time software

PSDL is a language for describing prototypes of real-time software systems. It is most useful for requirements analysis, feasibility studies, and the design of large embedded systems. PSDL has facilities for recording and enforcing timing constraints, and for modeling the control aspects of real-time systems using nonprocedural control constraints, operator abstractions, and data abstractions. The language has been designed for use with an associated prototyping methodology. PSDL prototypes are executable if supported by a software base containing reusable software components in an underlying programming language (e.g. Ada)     

Towards a Formal Semantics for UML/MARTE State Machines Based on Hierarchical Timed Automata

UML is a widely-used,general purpose modeling language.But its lack of a rigorous semantics forbids the thorough analysis of designed solution,and thus precludes the discovery of significant problems at design time.To bridge the gap,the paper investigates the underlying semantics of UML state machine diagrams,along with the time-related modeling elements of MARTE,the profile for modeling and analysis of real-time embedded systems,and proposes a formal operational semantics based on extended hierarchical timed automata.The approach is exemplified on a simple example taken from the automotive domain.Verification is accomplished by translating designed models into the input language of the UPPAAL model checker.     

UML嵌入式系统设计

UML是当今最流行的标准建模语言,嵌入式系统是以应用为中心、以计算机技术为基础的专用计算机系统,是软件和硬件的综合体;而嵌入式系统设计的好坏是数字商品成功荫关键。本文重点讨论UML建模中重要的概念,以及如何在嵌入式系统设计中使用UML OOD建模技术,并结合实例“微波炉小灯”演示采用UML的嵌入式系统设计过程。     

Clock constraint specification language: specifying clock constraints with UML/MARTE

The Object Management Group (OMG) unified modeling language (UML) profile for modeling and analysis of real-time and embedded systems (MARTE) aims at using the general-purpose modeling language UML in the domain of real-time and embedded (RTE) systems. To achieve this goal, it is absolutely required to introduce inside the mainly untimed UML an unambiguous time structure which MARTE model elements can rely on to build precise models amenable to formal analysis. The MARTE Time model has defined such a structure. We have also defined a non-normative concrete syntax called the clock constraint specification language (CCSL) to demonstrate what can be done based on this structure. This paper gives a brief overview of this syntax and its formal semantics, and shows how existing UML model elements can be used to apply this syntax in a graphical way and benefit from the semantics.     

UML嵌入式系统设计

UML是当今最流行的标准建模语言,嵌入式系统是以应用为中心、以计算机技术为基础的专用计算机系统,是软件和硬件的综合体;而嵌入式系统设计的好坏是数字商品成功的关键。本文重点讨论UML建模中重要的概念,以及如何在嵌入式系统设计中使用UMLOOD建模技术,并结合实例微波炉小灯演示采用UML的嵌入式系统设计过程。     

基于UML的SoC建模设计方法研究

随着集成电路制造工艺的发展,嵌入式计算机应用向着SoC的方向发展。为了适应制造工艺对SoC设计能力的要求,提高SoC的设计效率,成为了很紧迫的必要任务。采用统一的SoC系统级建模语言SystemC、软/硬件协同设计技术、基于IP核复用等技术的SoC设计流程,在一定程度上满足了SoC设计要求。在现有SoC设计流程基础上,结合UML的模型驱动框架（MDA）设计方法,在当前的SoC设计流程的系统需求规约描述、硬件实时反应式系统建模、软件模块设计实现中采用UML针对SoC的轻量型扩展特性,可以很大程度地改进提高SoC的设计流程效率。     

Modeling distributed real-time applications with specification PEARL

The methodology of hardware/software co-design of embedded control systems with Specification PEARL is presented. Hardware and software are modeled with the language Specification~PEARL, which has its origins in standard Multiprocessor~PEARL. Its usefulness is enhanced for modeling hierarchical and asymmetrical multiprocessor systems, and by additional parameters for schedulability analysis. Graphical symbols are introduced for its constructs to enable graphical modeling while maintaining the semantical background. It is meant to be a superlayer for programs, based on the PEARL programming model. To model program tasks, Timed State Transition Diagrams have been defined. The model of a co-designed system is verified for feasibility with co-simulation. The resulting information should be used when considering changes in a current design with the goal of producing a temporally feasible model. To support dynamic re-configurations, configuration management is introduced into the models. Since UML is becoming a de facto standard also for designing embedded control systems, and since Timed State Transition Diagrams and State Chart Diagrams share great similarity, an interface of the methodology to UML 2 is defined, using UML's extension mechanisms.     

Validation of static properties in unified modeling language models for cyber physical systems

Cyber physical systems (CPSs) can be found nowadays in various fields of activity. The increased interest for these systems as evidenced by the large number of applications led to complex research regarding the most suitable methods for design and development. A promising solution for specification, visualization, and documentation of CPSs uses the Object Management Group (OMG) unified modeling language (UML). UML models allow an intuitive approach for embedded systems design, helping end-users to specify the requirements. However, the UML models are represented in an informal language. Therefore, it is difficult to verify the correctness and completeness of a system design. The object constraint language (OCL) was defined to add constraints to UML, but it is deficient in strict notations of mathematics and logic that permits rigorous analysis and reasoning about the specifications. In this paper, we investigated how CPS applications modeled using UML deployment diagrams could be formally expressed and verified. We used Z language constructs and prototype verification system (PVS) as formal verification tools. Considering some relevant case studies presented in the literature, we investigated the opportunity of using this approach for validation of static properties in CPS UML models.     

The COMPLEX methodology for UML/MARTE Modeling and design space exploration of embedded systems

The design of embedded systems is being challenged by their growing complexity and tight performance requirements. This paper presents the COMPLEX UML/MARTE Design Space Exploration methodology, an approach based on a novel combination of Model Driven Engineering (MDE), Electronic System Level (ESL) and design exploration technologies. The proposed framework enables capturing the set of possible design solutions, that is, the design space, in an abstract, standard and graphical way by relying on UML and the standard MARTE profile. From that UML/MARTE based model, the automated generation framework proposed produces an executable, configurable and fast performance model which includes functional code of the application components. This generated model integrates an XML-based interface for communication with the tool which steers the exploration. This way, the DSE loop iterations are efficiently performed, without user intervention, avoiding slow manual editions, or regeneration of the performance model. The novel DSE suited modelling features of the methodology are shown in detail. The paper also presents the performance model generation framework, including the enhancements with regard the previous simulation and estimation technology, and the exploration technology. The paper uses an EFR vocoder system example for showing the methodology and for demonstrative results.     

实时系统的面向方面模型

基于UML的实时系统面向方面模型，能够把实时关注从系统中分离出来，形成一个独立于系统的时间方面，实现时间方面的并发设计和系统时间特性的统一管理。面向方面编程（AOP）技术允许把设计好的时间方面根据特定需要重新织入系统，组合为实时系统。模型扩展了UML来表达AOP技术和时间概念，并从系统的静态结构模型、动态行为模型和时间方面的织入等几部分建模实时系统。一个电梯控制系统例子充分说明这种设计过程。     

Model transformations in the UPES/UPSoC development process for embedded systems

Model-based development (MBD) aims at combining modeling languages with model transformers and code generators. Modeling languages, like profiles of the Unified Modeling Language (UML), are increasingly being adopted for specific domains of interest to alleviate the complexity of platforms and express domain concepts effectively. Moreover, system development processes based on automatic model transformations are widely required to improve the productivity and quality of the developed systems. In this paper, we show how MBD principles and automatic model transformations provide the basis for the unified process for embedded systems (UPES) development process and its unified process for system-on-chip (SoC) (UPSoC) subprocess. They have been defined to foster in a systematic and seamless manner a model-based design methodology based on the UML2 and UML profiles for the C/SystemC programming languages, which we developed to improve the current industrial system design flow in the embedded systems and system-on-chip area. This work is supported in part by the project Model-driven methodologies and techniques for embedded systems design and analysis based on UML, Abstract State Machines, and SystemC at STMicroelectronics, AST R&I of Agrate Brianza (MI), Italy.     

Integrating Data Flow Equations with UML/Realtime

Object-oriented (OO) modeling languages, tools, and methods more and more attract the interest of embedded (real-time) system developers. This is especially true if embedded (real-time) system software has to cooperate with interactive multimedia software, as it is more and more the case in automotive systems. It is still an open question whether and how the standard OO modeling language UML and its accompanying tools have to be adapted to the regarded application domain. This paper evaluates the development of a rapid prototype for an air condition controller with the popular CASE tool Rational Rose/RT^®. We point out some weaknesses of the presented solution and propose an extension to Rose/RT^®, which overcomes the weaknesses by combining Rose/RTs UML dialect with data flow equations.     

基于UML和平台的嵌入式系统设计方法研究

针对嵌入式系统设计和开发的特点和需求的不断提高导致设计开发的复杂性,研究了将UML和平台结合进行嵌入式系统设计的一种方法,使用UML描述平台细节和所提供的功能;利用UML的扩展特性建立了一种UML平台profile,包含建立新的构造类、构造关系、标签值和约束;并将这种UML和平台相结合的设计方法应用在嵌入式系统实例上,选择了组成嵌入式系统实例的硬件和软件平台,针对实例平台不同的服务层次建立了面向应用建模服务的相应实例平台模型,使用了静态图和动态图表示了这种平台模型,并且描述了实例平台模型的一种应用.     

Dynamic Meta Modeling with Time: Specifying the Semantics of Multimedia Sequence Diagrams

UML offers different diagram types to model behavior and dynamics of software systems. In some domains like embedded real-time systems or multimedia systems, it is necessary to include specifications of time since the correctness of these applications depends on the fulfillment of temporal requirements in addition to functional requirements. UML thus already incorporates language features to model time and temporal constraints. Such model elements must have an equivalent in the semantic domain. We have proposed Dynamic Meta Modeling (DMM) as a means for the specification of the formal operational semantics of UML models by applying graph transformation to the meta modeling of dynamic behavior. Within this paper, we extend this approach to also account for time by building on timed graph transformations. We apply these concepts to the domain of multimedia application modeling in which we adopt UML sequence diagrams. The DMM rules with time then specify an interpreter that can be used to analyze or test a model of multimedia sequence diagrams.     

Generating heterogeneous executable specifications in SystemC from UML/MARTE models

Modeling and analysis of real-time embedded system is becoming an important area of research nowadays. In this context, the UML/MARTE profile has been introduced to support the specification, design, and verification stages in the development process. It provides a wide set of facilities to capture the information required in the refinement steps throughout the design flow. To carry out the actions involved in these design steps, MARTE-based tools and methodologies are required. This paper presents a methodology to automatically generate SystemC heterogeneous executable specifications from generic MARTE models. To generate these specifications, the information included in the MARTE models is extracted to discover the system structure and hierarchy. A subset of the concurrency and communication features of the MARTE profile is used for this purpose. Then, automatic generation of the executable specification is possible. The code implementing the corresponding behavior can be easily integrated into the executable model. This design methodology proposes a refinement flow in order to perform the design steps before deciding the final system implementation.