一种基于过程级编程模型的可重构片上系统设计方法

可重构片上系统是一种兼具功能灵活性与高运算速度的新型计算平台,是面向未来嵌入式应用市场复杂需求的技术解决方案,但复杂、困难的设计过程必将阻碍它的广泛应用与进一步发展.针对当前可重构片上系统设计过程中编程不透明、可重构资源难以有效利用等问题,结合可编程器件能够根据应用特性动态配置芯片体系结构的特点,提出并实现了一套基于过程级透明编程模型的软硬件协同设计方法.在编程模型框架内,系统设计人员通过调用已根据应用特性进行优化的软硬件协同函数库,即可利用高级语言完成系统功能描述;动态软硬件划分算法在程序运行时对其进行划分,选择、调度需要转换到软件或硬件实现的库函数,并通过动态链接器实时切换函数的运行方式,从而形成一个由功能描述到系统实现的自动化流程.实验及测试结果验证了该方法的可行性和高效性.     

基于过程级编程模型的软硬件协同设计框架

当前动态可重构计算系统对程序员编程不透明,且动态可重构资源难以有效利用。针对上述问题,提出一种基于过程级透明编程模型的软硬件协同设计框架。在该框架内,软件开发人员对软硬件协同函数库进行调用,即可用C语言完成系统功能描述。动态软硬件划分算法在程序运行时进行划分,自动选择并调度需要转换到软件或硬件的库函数,通过动态链接器实时切换函数的运行方式,实现由功能描述到系统实现的自动化流程。     

支持动态可重构的软/硬件统一多线程编程模型

针对可重构系统中的数据流驱动应用,提出支持动态可重构的软/硬件统一多线程编程模型SHUMDR及其层次化实现.通过硬件线程接口设计、操作系统内核扩展,便于设计人员以统一的线程视图描述应用的软硬件划分.以数据加密/解密为例进行测试的结果表明,统一线程抽象带来的时间开销和空间资源占用率较小,该模型在探索编程灵活性的同时,能够有效地兼顾硬件的效率.     

支持过程级动态软硬件划分的RSoC设计与实现

目前,可重构计算平台所支持的动态软硬件划分粒度多处于线程级或指令级,但线程级划分开销太大,而指令级划分又过于复杂,因此很难被用于实际应用之中。本文设计并实现了一种支持过程级动态软硬件划分的可重构片上系统(RSoC),提出了一种过程级硬件透明编程模型,给出了过程级的硬件封装方案;在分析软硬件过程根本区别的基础上,针对硬件过程开发了专门的管理模块,并利用部分动态重构等技术,实现了硬件过程的动态配置。实验表明该系统能够较好的支持过程级的动态软硬件划分,实现了节省资源、简化设计,提高性能等目的。     

计算机辅助可重构制造系统设计

可重构制造系统是为了快速而准确地提供响应新的高层需求所需的生产能力和生产同一零件族内的新零件所需的制造功能，从一开始就设计成可面向系统级和生产资源级快速而又以有竞争力的成本重构的制造系统，文中分析了可重构制造系统的设计方法及其特征，提出了计算机辅助可重构制造系统设计这一新的研究方向，说明了包括动态适应学习识别机制，建模分析与性能优化，专家系统、集成设计等模块的设计机辅助可重建制造系统设计的流程，实现了可重构制造系统的集成设计。     

基于CPCI的动态可重构数据采集系统

本文基于CPCI和SOPC技术,提出了动态可重构数据采集系统的设计思想,详细描述了系统可重构软硬件的实现,开发了基于CPCI的动态可重构采集系统,指出了动态可重构采集系统的应用前景.     

FPGA动态可重构理论及其研究进展

近年来,随着微电子技术和计算机技术的发展,尤其是大规模现场可编程门阵列FPGA的出现,实时电路重构技术逐渐成为国际学术界的研究热点;基于FPGA的重构系统具有自适应、自主修复特性,在空间应用中具有非常重要的作用;文章介绍了基于FP-GA动态可重构技术的原理、分类,重点讨论了动态可重构的实现方法及两种技术,并给出了系统重构设计的流程,同时,介绍了基于FPGA动态可重构技术已取得的成功应用,最后展望了FPGA动态可重构技术的发展前景,并指出了有待解决的问题.     

基于权重可变免疫算法的动态可重构任务划分

基于FFGA的动态可重构系统能够在系统运行期间通过动态调整硬件资源来适应应用问题,从而满足嵌入式系统对性能、灵活性和成本越来越严格的要求.系统可动态加载配置文件的特点给系统软硬件任务的划分带来了新的问题.在充分考虑动态可重构系统特点的基础上,通过动态改变目标函数权重系数来适应可重构的变化,并运用于免疫算法对系统软硬件任务进行划分.实验结果表明,提出的划分方法除了能更贴近实际的系统外还具有较高的性能.     

基于FPGA的软硬件统一多任务模型及功能调度技术研究

为了解决工业控制计算机中的基于FPGA的可重构模块的任务调度问题,提出了一种基于FPGA的软硬件统一多任务模型建立及功能调度方法。该方法中包括基于FPGA的软硬件统一多任务模型建立及功能调度方法的设计思路和实现过程。该方法通过对软件和硬件任务特性以及FPGA的在线配置与部分动态重构的研究分析,建立了软硬件任务的统一模型,从而实现了对软硬件任务的统一调度,有效的提升了资源的利用效率。该方法应经投入应用,在应用过程中取得了良好的效果。     

基于混沌PSO的动态可重构系统软硬件划分

软硬件划分是动态可重构系统软硬件协同设计中的关键技术之一,如何兼顾划分效率和划分效果,达到两者的最佳结合是软硬件划分的主要问题.在考虑动态部分重构及重构延时等特征的基础上,提出一种微粒群优化算法与混沌优化算法相结合的混沌微粒群软硬件划分方法.该算法使用基于实数编码的微粒群优化算法执行全局搜索,再根据搜索结果采用混沌优化算法执行局部搜索,具有较强的全局搜索和跳出局部最优的能力.仿真实验表明,该算法比标准微粒群算法和遗传算法具有更好的有效性和快速性,能够有效地实现应用任务图到可重构系统的时空映射.     

一种基于RSOC的软硬件协同设计方法研究

针对可重构片上系统(RSOC)应用设计复杂、编程困难的问题,提出了一种软硬件协同设计方法。该方法整体框架基于特定功能模块的软硬件协同函数。给出了方法的基本流程、涉及的关键技术及实现方式,并验证了关键部分的设计方案及可行性。该方法为目标应用设计人员屏蔽了特定功能模块的软硬件实现细节,提高了基于RSOC应用的运行效率和灵活性。     

支持硬件透明编程模型的动态可重构系统的设计与实现*

以Java作为可重构系统描述语言,提出了一种方法级的硬件透明编程模型,给出了硬件方法封装方式和软硬件方法动态链接过程。程序设计者调用软件方法进行应用开发,虚拟机根据软硬件划分结果动态加载并链接相应的硬件方法,从而达到简化编译器和综合工具以及屏蔽底层物理细节的目的。实验结果表明上述编程模型能够支持硬件透明编程,同时系统性能得到了明显的改善。     

Structured synthesis of MEMS using evolutionary approaches

In this paper, we discuss the hierarchy that is involved in a typical MEMS design and how evolutionary approaches can be used to automate the hierarchical synthesis process for MEMS. The paper first introduces the flow of a structured MEMS design process and emphasizes that system-level lumped-parameter model synthesis is the first step of the MEMS synthesis process. At the system level, an approach combining bond graphs and genetic programming can lead to satisfactory design candidates as system-level models that meet the predefined behavioral specifications for designers to trade off. Then at the physical layout synthesis level, the selection of geometric parameters for component devices and other design variables is formulated as a constrained optimization problem and addressed using a constrained genetic algorithm approach. A multiple-resonator microsystem design is used to illustrate the integrated design automation idea using these evolutionary approaches.     

A high level FPGA-based abstract machine for image processing

Image processing requires high computational power, plus the ability to experiment with algorithms. Recently, reconfigurable hardware devices in the form of field programmable gate arrays (FPGAs) have been proposed as a way of obtaining high performance at an economical price. At present, however, users must program FPGAs at a very low level and have a detailed knowledge of the architecture of the device being used. They do not therefore facilitate easy development of, or experimentation with, image processing algorithms. To try to reconcile the dual requirements of high performance and ease of development, this paper reports on the design and realisation of an FPGA based image processing machine and its associated high level programming model. This abstract programming model allows an application developer to concentrate on the image processing algorithm in hand rather than on its hardware implementation. The abstract machine is based on a PC host system with a PCI-bus add-on card containing Xilinx XC6200 series FPGA(s). The machine's high level instruction set is based on the operators of image algebra. XC6200 series FPGA configurations have been developed to implement each high level instruction.     

基于SDL语言的VxWorks嵌入式操作系统的具体实现

随着嵌入式系统通信协议的复杂性急剧提高，迫使工程师们去寻找一种效率更高的设计工具来完成工作，而SDL作为一种图形化的设计满足了这种需要，因此RTOS-SDL相结合的思路应运而生。主要说明了把SDL应用在VxWorks中的步骤和具体实现中遇到的问题，以及编程中的一些技巧。而且经试验表明，采用这种方法不但可以完成原先的需求，而且还可以在有限的时间内完成程序的编写，提高工作效率，对于SDL和嵌入式系统的结合具有很好的参考价值。     

A framework for collaborative top-down assembly design

This paper presents a new system framework for collaborative top-down assembly design. Different from current computer-aided design (CAD) systems, the framework allows a group of designers to collaboratively conduct product design in a top-down manner. In our framework, a multi-level and distributed assembly model is adopted to effectively support collaborative top-down assembly design. Meanwhile, fine-granularity collaborative design functionalities are provided. First, the coupled structural parameters involved in the distributed skeleton models of the product can be collaboratively determined by the correlative designers based on fuzzy and utility theory. Second, agent based design variation propagation is achieved to ensure the consistency of the multi-level and distributed assembly model during the whole design process. Third, collaborative design of assembly interfaces between the components assigned to different designers is supported. The prototype implementation shows that our framework works well for supporting practical collaborative top-down assembly design.     

One MEMS design tool with maximal six design flows

This paper presents one MEMS design tool with a total six of design flows, which makes it possible that the MEMS designers choose the most suitable design flow for their specific devices. The design tool is divided into three levels and interconnected by six interfaces. The three levels are the lumped-element model based system level, finite element analysis based device level and process level, which cover nearly all modeling and simulation functions for MEMS design. The six interfaces are proposed to automatically transmit the design data between every two levels, thus the maximal six design flows could be realized. The interfaces take the netlist, solid model and layout as the data inlet and outlet for the system, device and process level respectively. The realization of these interfaces are presented and verified by design examples, which also proves that enough flexibility in the design flow can really increase the design efficiency.     

A template system for the efficient compilation of domain abstractions onto reconfigurable computers

Past research has addressed the issue of using FPGAs as accelerators for HPC systems. Such research has identified that writing low level code for the generation of an efficient, portable and scalable architecture is challenging. We propose to increase the level of abstraction in order to help developers of reconfigurable accelerators deal with these three key issues. Our approach implements domain specific abstractions for FPGA based accelerators using techniques from generic programming. In this paper we explain the main concepts behind our system to Design Accelerators by Template Expansions (DATE). The DATE system can be effectively used for expanding individual kernels of an application and also for the generation of interfaces between various kernels to implement a complete system architecture. We present evaluations for six kernels as examples of individual kernel generation using the proposed system. Our evaluations are mainly intended to provide a proof-of-concept. We also show the usage of the DATE system for integration of various kernels to build a complete system based on a Template Architecture for Reconfigurable Accelerator Designs (TARCAD).