共查询到17条相似文献,搜索用时 93 毫秒
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为了提高加法器的运算速度,提出了一种新型并行整数加法算法——桶形整数加法算法。该加法器以半加器为基础,将并行与迭代反馈思想相结合,根据每轮迭代后进位链的值判断是否已经累加结束,可以在保持低功耗的同时提高运算速度。仿真结果表明,该桶形整数加法器在面积少量增加的基础上,速度提高明显。 相似文献
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针对目前存在的缩1码模2~n+1加法器的优缺点,设计出一个有效的基于进位选择的缩1码模2~n+1加法器。在模加法器的进位计算中,采用进位选择计算代替传统的进位计算,进位计算前缀运算量明显减少。分析和实验结果表明,对于比较大的n值,进位选择缩1码模2~n+1加法器在保持较高运算速度的前提下,有效地提高了集成度。 相似文献
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本文介绍了用原理图输入方法设计一款图象处理ASIC芯片中乘加单元的核心运算部件——32位超前进位加法器,出于速度(时延)和面积折衷优化考虑,它以四位超前进位加法器和四位超前进位产生器为基本设计单元级联而成,因此该电路具有速度和面积的折衷优势。选择原理图输入方法,是考虑到本电路复杂度不高,而原理图输入可控性好,效率高,可靠性强且直观,可以熟悉较底层的结构。文章先给出电路的设计实现,并且是先设计四位超前进位加法器,再提出32位超前进位加法器的设计思想和设计原理,然后再通过测试文件的逻辑验证正确。本设计的所有内容,都将在SUN工作站上Cadence工具Schematic Composer中完成。 相似文献
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描述了一款适用于超长指令字数字信号处理器的64位加法器的设计。该加法器高度可重构,可以支持2个64位数据的加法运算、4个32位数据的加法运算、8个16位数据的加法运算以及16个8位数据的加法运算。它结合了Brent-Kung对数超前进位加法器和进位选择加法器的优点,使得加法器的面积和连线减少了50%,而延时与加法器的长度的对数成正比。仿真结果表明,在典型工作条件下,采用0.18μm工艺库标准单元,其关键路径的延时为0.83ns,面积为0.149mm2,功耗仅为0.315mW。 相似文献
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本文介绍了在某微处理器研制中设计的一种地址生成单元的加法电路。为提高地址转换速度,其进位电路中采用了动态门和多米诺逻辑。结果表明,在1.8v、0.18μm工艺下进行电路模拟,进行一次加法进位传递的时间为466ps。 相似文献
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基于可编程器件的加法器结构研究 总被引:1,自引:0,他引:1
加法运算是数字信号处理最基本的运算,随着各种可编程逻辑器件在数字信号处理领域越来越多的应用,高速加法器在可编程器件上的研究应该得到人们的重视。文章根据VirtexTM-E器件的特点,分析了各种常用加法器结构在可编程器件上实现的可行性和将遇到的问题,给出了一种适于可编程器件的行波进位/跳跃进位加法器实现形式。 相似文献
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基于算术加法测试生成,提出了VLSI中加法器的一种自测试方案:加法器产生自身所需的所有测试矢量.通过优化测试矢量的初值改进这些测试矢量,提高了其故障侦查、定位能力.借助于测试矢量左移、逻辑与操作等方式对加法器自测试进行了设计.对8位、16位、32位行波、超前进位加法器的实验结果表明,该自测试能实现单、双固定型故障的完全测试,其单、双故障定位率分别达到了95.570%,72.656%以上.该自测试方案可实施真速测试且不会降低电路的原有性能,其测试时间与加法器长度无关. 相似文献
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This paper presents CMOS circuit designs of a ternary adder and a ternary multiplier,formulated using transmission function theory.Binary carry signals appearing in these designs allow conventional look-ahead carry techniques to be used.compared with previous similar designs,the circuits proposed in this paper have advantages such as low dissipation,low output impedance,and simplicity of construction. 相似文献
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The adders are the vital arithmetic operation for any arithmetic operations like multiplication, subtraction, and division. Binary number additions are performed by the digital circuit known as the adder. In VLSI (Very Large Scale Integration), the full adder is a basic component as it plays a major role in designing the integrated circuits applications. To minimize the power, various adder designs are implemented and each implemented designs undergo defined drawbacks. The designed adder requires high power when the driving capability is perfect and requires low power when the delay occurred is more. To overcome such issues and to obtain better performance, a novel parallel adder is proposed. The design of adder is initiated with 1 bit and has been extended up to 32 bits so as verify its scalability. This proposed novel parallel adder is attained from the carry look-ahead adder. The merits of this suggested adder are better speed, power consumption and delay, and the capability in driving. Thus designed adders are verified for different supply, delay, power, leakage and its performance is found to be superior to competitive Manchester Carry Chain Adder (MCCA), Carry Look Ahead Adder (CLAA), Carry Select Adder (CSLA), Carry Select Adder (CSA) and other adders. 相似文献
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Multiple-valued quantum logic circuits are a promising choice for future quantum computing technology since they have several advantages over binary quantum logic circuits. Adder/subtractor is the major component of the ALU of a computer and is also used in quantum oracles. In this paper, we propose a recursive method of hand synthesis of reversible quaternary full-adder circuit using macro-level quaternary controlled gates built on the top of ion-trap realizable 1-qudit quantum gates and 2-qudit Muthukrishnan–Stroud quantum gates. Based on this quaternary full-adder circuit we propose a reversible circuit realizing quaternary parallel adder/subtractor with look-ahead carry. We also show the way of adapting the quaternary parallel adder/subtractor circuit to an encoded binary parallel adder/subtractor circuit by grouping two qubits together into quaternary qudit values. 相似文献