高效缩1码模2n+1加法器设计与优化 |
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引用本文: | 吕晓兰.高效缩1码模2n+1加法器设计与优化[J].测控技术,2014,33(2):127-129. |
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作者姓名: | 吕晓兰 |
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作者单位: | 广东石油化工学院 计算机与电子信息学院 |
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基金项目: | 广东省自然科学基金重点项目(S2011020002735);广东省教育部产学研结合项目 (2011A090200088) |
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摘 要: | 针对目前存在的缩1码模2~n+1加法器的优缺点,设计出一个有效的基于进位选择的缩1码模2~n+1加法器。在模加法器的进位计算中,采用进位选择计算代替传统的进位计算,进位计算前缀运算量明显减少。分析和实验结果表明,对于比较大的n值,进位选择缩1码模2~n+1加法器在保持较高运算速度的前提下,有效地提高了集成度。
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关 键 词: | 余数系统 模加法器 缩码 VLSI |
Design and Optimization of Diminished-One Modulo 2n+1 Adder |
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Abstract: | An efficient diminished-one modulo 2n+1 adder is proposed.The diminished modulo adders are designed with a sparse parallel-prefix carry computation stage,and only some of the carries of the modulo 2n+1 addition is computed.The carry computation unit is far simpler,since it requires significantly less prefix operators.The analytical and experimental results indicate that the resulting diminished-one modulo 2n+1 adder can be implemented in smaller area compared to earlier proposals,while maintaining a high operation speed for sufficiently wide operands. |
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Keywords: | residue number system(RNS) modulo adder diminished-one VLSI |
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