宽带连续可调程控增益放大器的设计

本设计采用12位具有四象限乘法功能的DAC及运放等宽频带器件进行了电路设计,配合三级放大电路,使该放大器具有0-5M的带宽。在此带宽范围内,其增益可实现0.1～1000范围内连续可调,本文设计的增益放大器具有良好的线性度及千分之一的分辨率。采用运放、DAC、模拟开关等小规模集成电路进行系统设计,降低了成本。     

高性能四通道数字可编程序运算放大器HA—2400

ＨＡ－２４００是一种具有四个相同输入级，一个输出级，输入与输出通过数字可控模拟开关相连的高性能组合运算放大器，该运放具有高的输入阻抗，低的失调电流，高的转换速率，宽的增益带宽，加之灵活的数字可控输出的功能，使各种新型电路的应用变成了现实。     

基于AD603程控增益大功率宽带直流放大器的设计

采用低噪声增益可程控集成运算放大器AD603和高频三极管2N2219和2N2905等器件设计了宽带直流放大器,该放大器具有增益可程控、功率高、频带宽、带宽可选择等特点。输入级采用两级AD603级联,以提高增益控制范围;中间级采用分立元件制作了高输出功率放大器,输出级设计了两路通频带分别为0～5MHz以及0～10MHz的低通滤波器实现带宽的可预置,通过51单片机可以对放大器增益和带宽进行控制。此外对提高直流放大器的各种性能指标提出了多种具体措施,在自动化要求较高的系统中具有很好的实用性。     

高性能四通道数字可编程序运算放大器HA－2400

ＨＡ－２４００是一种具有四个相同输入级，一个输出级，输入与输出通过数字可控模拟开关相连的高性能组合运算放大器。该运放具有高的输入阻抗，低的失调电流，高的转换速率，宽的增益带宽，加之灵活的数字可控输出的功能，使各种新型电路的应用变成了现实。     

一种低电压、高速CMOS运放的设计与仿真

本文设计了一种基于流水线ADC系统应用的低电压、高速运算放大器,该运放使用折叠式共源共栅结构、稳定的电压偏置电路、新型的共模反馈电路,使运放达到更高的性能.设计基于BSIM3V3 Spice模型,采用SMIC标准0.18 μm CMOS工艺,用Cadence的Spectre工具对整个电路进行仿真.在1.8 V单电源电压、2 pF电容负载的工作条件下,仿真结果显示:直流开环增益为82 dB,其单位增益带宽为260 MHz,相位裕度60°,压摆率100 V/μs,建立时间约10 ns,功耗只有3.6 mW,达到了设计要求.     

基于CCⅡ±的差分放大器

本文提出了一种新的由第二代电流传送器构成的差分放大器,并通过分析证明该电路具有高共模抑制比和高差模增益及带宽。     

宽带高增益精密程控放大器设计

回顾了几种程控放大器的结构，给出了一种宽带高增益精密程控放大器的设计方法，该方法避免了对精密衰减器或复杂电阻网络的过高要求。     

程控增益放大器及其与微机的接口

本文讨论了智能仪器模拟通道中放大器增益控制的几种方案，着重分析了一种由Ｄ／Ａ转换器构成的程控增益放大器的工作原理及其与微机的接口。     

半导体放大器中的反馈分析

半导体放大器在光通信网中最主要的优势是用于线路放大器上，在大多数的放大器系统中，为了保证得到良好的增益效果，一般加入了反馈机制来对放大器增益进行提高和控制，本文即针对于半导体放大器中的反馈机制展开分析，探索半导体放大器的工作原理和反馈特性，并应用到为今后的科研与工作之中。     

一种带新型共模反馈电路的全差分放大器设计

总结了全差分运算放大器的优缺点,分析了全差分运算放大器中共模反馈的原理,共模反馈电路的4种典型的实现方式,计算了它们的小信号增益,并设计了一种带新型共模反馈电路的全差分运算放大器,它可以精确的控制输出共模电压,稳定在2.5V。     

激光回波小信号宽带放大器设计

设计了一款激光回波小信号宽带低噪声放大器。选用低噪声、高带宽电流反馈型差分运算放大器THS4509,采用两级放大电路结构以获得较大的放大倍数,利用传输线变压器实现输出信号由双端到单端转换。为减小噪声,采用过渡带特性最好的椭圆低通滤波器滤除带外噪声。经实验验证,该放大器具有40 dB放大倍数、120 MHz带宽和小于10 mV(pp)的系统噪声,能对各种反射率条件下不同目标反射回的微弱激光小信号进行有效放大,较好地解决了远距离和低反射率目标物体测距问题,实际测试测距量程可达450 m。     

An ultra-low-power,low-noise tunable electrocardiogram amplifier

The objective of this research work is to propose an innovative low-power, low-noise, tunable three-stage capacitive instrumentation amplifier, capable of receiving and magnifying the electrocardiogram (ECG) signals. This is done by adding an extra stage to the second stage of the conventional capacitive instrumentation amplifier. The results show similar midband gain with lesser capacitor usage and smaller chip occupancy area with provision of concurrent tunable gain and bandwidth. The proposed amplifier is designed and implemented using TSMC 0.18-μm CMOS technology scale under a 1-V supply voltage with the simulation process carried out using Cadence Virtuoso tool. Post-layout simulation results show that the amplifier has a tunable midband gain of 55 to 65.6 dB, low-cutoff frequency tuned from 377 mHz to 4.5 Hz and high-cutoff frequency tuned from 86.8 to 263.6 Hz. The simulated value of the input-referred noise and noise efficiency factor (NEF) of the amplifier are 9.6 μV_rms and 6.1, respectively, with the total power consumption of 71.2 nW.     

Low‐power and low‐noise complementary metal oxide semiconductor distributed amplifier using the gain‐peaking technique

This paper presents an improved topology for ultra‐low‐power complementary metal oxide semiconductor (CMOS) distributed amplifier (DA) based on modified folded cascode gain cells. The proposed CMOS‐DA can be applicable in low‐supply‐voltage applications, because of the use of folded gain cell's structure. The proposed DA decreases power consumption by employing the forward body biasing network, while maintains high gain. By using a gain‐peaking inductor at the gate of the transistor, the proposed DA structure achieved to the gain flatness in high frequencies while the bandwidth is improved as well. In addition, employing RC network at the body terminal improves the noise performance of the proposed DA. The DA architecture consists of three amplification stages. Detailed analysis is provided for the proposed folded cascode DA. According to the post‐layout simulation results of the proposed amplifier using a 0.13‐µm CMOS process, DA achieves power gain of 17.3 ± 0.8 dB in bandwidth of 14.5 GHz, a good input third‐order intercept point (IIP3) of +5.5 dBm. The minimum noise figure is 1.8–5 dB, and input and output return losses are less than −11.5 dB and −10 dB, respectively, and the proposed structure consumes 12 mW from a 0.5 V voltage supply. Copyright © 2016 John Wiley & Sons, Ltd.     

Design of an automatic gain control loop for high speed communication

This paper presents the design of an automatic gain control (AGC) loop for high-speed communication systems, which can be used in wired, wireless, or optical receiver. The design is performed in 130 nm SiGe BiCMOS technology. A Gilbert cell-based variable gain amplifier is designed, which shows approximately linear gain control with respect to the gain control voltage. The variable gain amplifier is followed by two fixed gain cascode amplifiers. Then, a full wave rectifier-based peak detector is designed and analyzed. To reduce the peak detector error, a compensation technique is applied. Finally, an operational amplifier is designed, which is used as voltage adder and comparator. The designed AGC loop is simulated with sinusoidal and pseudorandom binary sequence (prbs) input signal with high frequency signal of 1 to 30 GHz. The simulation results of the AGC loop show that a gain tuning range of 47 dB (−7 to 40 dB) is obtained in this design. It is also seen that the reference signal can be varied from 50 to 200 mV. This AGC works in the input voltage signal range between 3 mV peak and 230 mV peak, and the power dissipation of is 79 mW.     

Design of the CMOS inverter-based amplifier: A quantitative approach

The CMOS inverter can be used as an amplifier if properly biased in the transition region of its voltage-transfer characteristics (VTC). In this paper, the design of this amplifier is investigated with its merits and demerits illustrated and with the various trade-offs involved in its design discussed. Specifically, the following performance metrics are discussed quantitatively: gain, area, linearity, maximum allowable swing, bandwidth, stability, noise factor, impedance matching, and slew rate. Also, the effect of process, voltage, and temperature (PVT) variations are investigated. The optimum number of stages corresponding to the minimum area required for achieving a certain voltage gain is determined. The results obtained from the quantitative analysis and the simulation are discussed.     

大容性负载双极性高压功率放大器设计

设计了一种适合压电陶瓷驱动器等大容性负载动态应用的双极性高压功率放大器,它基于误差放大式原理,采用高压集成运放(PA89)驱动多组并联功率放大级的电路结构,在实现双极性高电压输出的同时具有很强的电流驱动能力.该放大器驱动等效电容为2.5μF的压电陶瓷驱动器时,能实现单端到地-500～+500V高压输出,电压增益40dB...     

Ultra‐low‐noise large‐bandwidth transimpedance amplifier

Equivalent input current noise and bandwidth are the most relevant parameters qualifying a low‐noise transimpedance amplifier. In the conventional topology consisting of an operational amplifier in a shunt‐shunt configuration, the equivalent input noise decreases as the feedback resistor (R_F), which also sets the gain, increases. Unfortunately, as R_F increases above a few MΩ, as it is required for obtaining high sensitivity, the bandwidth of the system is set by the parasitic capacitance of R_F and reduces as R_F increases. In this paper, we propose a new topology that allows overcoming this limitation by employing a large‐bandwidth voltage amplifier together with a proper modified feedback network for compensating the effect of the parasitic capacitance of the feedback resistance. We experimentally demonstrate, on a prototype circuit, that the proposed approach allows to obtain a bandwidth in excess of 100 kHz and an equivalent input noise of about 4 fA/ , corresponding to the current noise of the 1 GΩ resistor that is part of the feedback network. The new approach allows obtaining larger bandwidth with respect to those obtained in previously proposed configurations with comparable background noise. Copyright © 2014 John Wiley & Sons, Ltd.     

0.3‐V bulk‐driven programmable gain amplifier in 0.18‐µm CMOS

A new solution for an ultra low voltage bulk‐driven programmable gain amplifier (PGA) is described in the paper. While implemented in a standard n‐well 0.18‐µm complementary metal–oxide–semiconductor (CMOS) process, the circuit operates from 0.3 V supply, and its voltage gain can be regulated from 0 to 18 dB with 6‐dB steps. At minimum gain, the PGA offers nearly rail‐to‐rail input/output swing and the input referred thermal noise of 2.37 μV/Hz^1/2, which results in a 63‐dB dynamic range (DR). Besides, the total power consumption is 96 nW, the signal bandwidth is 2.95 kHz at 5‐pF load capacitance and the third‐order input intercept point (IIP₃) is 1.62 V. The circuit performance was simulated with LTspice. Copyright © 2016 John Wiley & Sons, Ltd.     

A 60‐GHz power amplifier design with on‐chip tunable load‐matching network and power detect in 90‐nm CMOS

This paper presents a 60‐GHz power amplifier with on‐chip varactor‐based tunable load‐matching networks and an embedded DC temperature‐sensor‐based power detector. The output power can be monitored by the DC temperature sensor, and load‐matching network can be tuned by regulating the control voltage of the varactors, which can be used for correcting unpredictable process, supply voltage, and temperature (PVT) variations and load mismatch. Measured results show that the small‐signal gain of the CMOS power amplifier is up to 6.5 dB at 52 GHz. The power amplifier achieves 5 dBm output P1dB and 7 dBm saturated output power with 4.5% maximun power added efficiency (PAE) at 1 V control voltage. By sweeping the control voltage of the varactors, the power amplifier can obtain the maximun power gain, which can be used to solve the load mismatch. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Preliminary design of 1 MW, Ku-band gyrotron traveling-wave amplifier

The preliminary design results of a 1-MW, Ku-band gyrotron traveling wave amplifier (gyro-TWA) are presented. Operating at the second cyclotron harmonic of the TE₁₁ mode, the amplifier characterizes good stability even in the case of no distributed losses loaded, which could potentially allow it to be operated at high average power. Large signal simulation shows that the amplifier can generate a saturated peak power of about 1 MW with efficiency of 26.6%, gain of 31 dB, and 3-dB bandwidth of about 1 GHz when driven by a 100 kV, 40 A electron beam with 5% axial velocity spread.