基于SoC芯片测试结构的研究

由于芯片规模的快速增长,给测试技术带来了新的挑战。结合系统芯片SoC测试结构的描述,对其核心部分测试外壳Wrapper和测试访问机制TAM做了论述,介绍了几类典型的测试访问机制TAM,分析其特点。同时对SoC的测试规划问题进行了讨论,指出了目前SoC测试面临的问题。     

嵌入式系统芯片级测试技术

针对目前流行的嵌入式芯片级测试技术,本文介绍了SoC测试技术的基本工作原理,利用93000 SoC测试系统,提出了相关测试内容、方法并得出最终测试结果.     

最新SOC测试的发展趋势

随着SOC芯片结构的复杂化，功能模块的多样化，SoC芯片的测试也面对诸多挑战，诸如测试资源和成本的兼顾。本文简单描述了现今SOC芯片的发展和趋势，以及相对应ATE测试系统的应对。     

SoC中混合信号的测试

随着经济社会的发展,人们对消费类电子的多媒体功能要求越来越高;这极大促进了SoC中混合信号工艺的运用,但是随之而来的是SoC在测试上遇到了前所未有的难题,因为混合信号电路的集成使他不同于纯数字电路IC的测试。SoC中混合信号的测试是SoC进一步发展的瓶颈,这对研究提出了紧迫的要求。介绍SoC中混合信号测试面临的主要问题,着重讨论了混合信号边界扫描测试,内置自测试方法(BIST)等测试手段及各自的特点。展望了SoC混合信号测试的研究方向。     

集成电路低峰值功耗研究

随着手持设备的兴起和芯片对晶片测试越来越高的要求。内建自测试的功耗问题引起了越来越多人的关注，本文对目前内建自测试的可测性设计技术进行了分析。并提出了折叠种子优化降低节点峰值功耗模型，通过调整种子结构和测。试向量的相关性的办法来避免过高的SoC测试峰值功耗，采取了屏蔽无效测试模式生成、提高应用测试向量之间的相关性以及并行加载向量等综合手段来控制测试应用，使得测试时测试向量的输入跳变显著降低．从而大幅度降低节点的峰值功耗。实验结果表明。该方案可以有效地避免BIST并行执行可能带来的过高峰值功耗。     

面向机载电子设备的自动化测试系统设计

随着机载电子设备复杂性的不断增长,测试的难度和工作量也在不断加大。为了有效应对测试带来的挑战,国外设备供应商研制了自动化测试系统。基于机载设备测试要求和系统工程方法,梳理了自动化测试系统应满足的测试场景,分析了系统需求,设计了硬件架构和软件架构,并专项设计了自动化测试软件的框架。在某机载型号研制中应用了设计方案,制造了测试系统并进行了验证。     

一种峰值功耗约束下的SoC蚁群测试调度算法

基于扫描链技术的SoC芯片测试可产生比正常使用模式下更大的功耗,这将会对器件可靠性产生不利影响,故在测试时需要将芯片测试功耗控制在允许峰值功耗之下.文中采用蚁群优化思路设计SoC测试调度算法,用于在峰值功耗和TAM总线最大宽度约束下降低SoC测试时间.实验结果表明,本方法优于先前已发表的相关方法.     

科利登新推出的Sapphire D-40系统能提供真正的可升级特性和模块化结构

SoC芯片功能的不断增加,再加上芯片尺寸不断缩小,新材料和新工艺的引进,要求工程验证及量产测试设备的复杂度和功能持续增加.除此之外,很多SoC芯片都应用在混合信号和无线应用上,进一步增加了复杂度.     

基于并行机制的边界扫描技术

在SoC测试时,测试功耗和测试成本是其可测性设计中最重要的一点要求.在分析了常见测试结构的测试功耗的基础上,提出了一种并行扫描机制的测试结构,包括访问机制的设计和测试控制器的设计.该方法可根据测试成本和测试功耗的要求,选择不同的构造方法.     

一种基于RS485的SoC产品测试平台的设计

介绍了一种以ARM高性能微处理器为核心,基于RS485总线的SoC产品自动化批量测试平台的设计方案。在对测试平台整体设计思路进行概述之后,介绍了其硬件组成及软件设计方法。经测试和实际运行表明,该测试平台能满足多种SoC产品的测试要求,能广泛应用于多种SoC产品的自动化批量测试中,提高生产效率,降低生产成本。     

An Efficient Block Entropy Based Compression Scheme for Systems-on-a-Chip Test Data

The emergence of the nanometer scale integration technology made it possible for systems-on-a-chip, SoC, design to contain many reusable cores from multiple resources. This resulted in higher complexity SoC testing than the conventional VLSI. To address this increase in design complexity in terms of data-volume and test-time, several compression methods have been developed, employed and proposed in the literature. In this paper, we present a new efficient test vector compression scheme based on block entropy in conjunction with our improved row-column reduction routine to reduce test data significantly. Our results show that the proposed method produces much higher compression ratio than all previously published methods. On average, our scheme scores nearly 13% higher than the best reported results. In addition, our scheme outperformed all results for each of the tested circuits. The proposed scheme is very fast and has considerable low complexity.     

A test set embedding approach based on twisted-ring counter with few seeds

Test data storage, test application time and test power dissipation increase dramatically for single stuck-at faults while tens of million gates are integrated in a System-on-a-Chip (SoC), which makes implementing fault testing for embedded cores based SoC become a challenging task. To further reduce test data storage, test application time and test power dissipation, this paper presents a new test set embedding approach based on twisted-ring counter (TRC) with few seeds. This approach includes two improvements. The first is that an efficient seed-selection algorithm is employed to exploit the high-density unspecified bits in the deterministic test set and so the test data storage for complete coverage of single stuck-at faults is minimized. The second is that a novel test-sequence-reduction scheme based on shifting seeds is proposed to reduce test application time that in turn reduces test power dissipation. Compared with the conventional approach, experiments on ISCAS’89 benchmark circuits show that the proposed approach requires 65% less test data storage, 68% shorter test application time and 67% less test power dissipation. Moreover, its hardware overhead is very small.     

Test response reuse-based SoC core test compression and test scheduling for test application time minimization

This paper presents a novel approach to system-on-a-chip (SoC) core test compression and test scheduling. Every test set is compressed through the test responses of its preceding core in preprocessing step by simulation. Consequently, under our method the test sets contain two parts: (1) the test sets that are compatible with the test responses of their individual preceding cores. This part can be removed from their original test sets, and (2) the test sets that none of the test vectors from them are compatible with the test responses of their individual preceding cores. On hardware implementation, only a couple of 2-1 MUXs are needed. The algorithms for reordering the sequences of core-under-tests and those of the test vectors for each corresponding core are outlined for optimal test compression results. It needs neither coder nor decoder, thus saving hardware overhead. Power-constrained SoC core test pipelining consumes less test application time. Hierarchical clustering-based SoC test scheduling can be implemented easily, and the hardware overhead is negligible. Experimental results on benchmark ISCAS 89 demonstrate that our method achieves significant improvement of test time and less ATE requirement over the previous methods, and it does not discount the fault coverage of each test set, moreover, the fault coverage for some test sets is improved instead.     

基于片上网络的系统芯片测试研究

文章介绍了基于片上网络对系统芯片进行测试的原理和实例，这是一种新的设计方法。首先讨论了未来系统芯片存在的各方面测试挑战，并提出了基于片上网络结构的解决方案。其次，在OSI网络堆栈参考模型的基础上．提出了面向测试的片上网络协议堆栈以及对应的测试服务。最后，介绍了基于片上网络的模块化测试方法。     

基于FDR码改进分组的SoC测试数据压缩方法

文章提出一种基于FDR码改进分组的SoC测试数据压缩方法.经过对原始测试集无关位的简单预处理,提高确定位0在游程中的出现频率.在FDR码的基础上,改进其分组方式,通过理论证明其压缩率略高于FDR编码,尤其是短游程的压缩率.用C语言编写程序模拟两种编码方法的软件实现程序,实验结果证明了改进分组的FDR编码方法的有效性和高压缩性.     

航空发动机试验测试及数据管理技术研究

我国航空发动机技术经过多年的发展,取得了巨大的进步,已经积累了大量的试验经验和测试数据,但是新时代航空发动机对测试技术提出了更高的要求,积极推动试验测试技术的发展势在必行.本文将首先介绍航空发动机试验测试技术的发展,分析测试技术的特点;其次将研究基于试验测试技术特点的试验数据管理的需求、特点和思路,对航空发动机试验测试技术特点和测试数据管理技术有全面的认识.     

Core-unified soc test data compression and application

The pattern run-length coding test data compression approach is extended by introducing don’t care bit (x) propagation strategy into it. More than one core test sets for testing core-based System-on-Chip (SoC) are unified into a single one, which is compressed by the extended coding technique. A reconfigurable scan test application mechanism is presented, in which test data for multiple cores are scanned and captured jointly to make SoC test application more efficient with low hardware overhead added. The proposed union test technique is applied to an academic SoC embedded by six large ISCAS’89 benchmarks, and to an ITC’ 02 benchmark circuit. Experiment results show that compared with the existing schemes in which a core test set is compressed and applied independently of other cores, the proposed scheme can not only improve test data compression/decompression, but also reduce the redundant shift and capture cycles during scan testing, de-creasing SoC test application time effectively.     

关于条形测试的组装技术(英文)

在过去的几年中,许多世界领先的半导体制造厂家及组装测试分包商开始了在形成完整的器件或封装体之前对引线框架、条形及板形器件的测试。类似的BIST,DFT和所有用途的更高水平的并行测试仪的测试技术的进展,将加速矩阵及条形测试的趋势。由于更多的制造厂家采用了条形测试技术,从而需要更高的生产效率和灵活性,以应对金属引线框架器件增加成本的压力和接触最新式的芯片尺寸封装几何形状难题的双重挑战。另外,新的组装特性必须考虑到它们与实现条形测试适用性的关系。分析了条形测试方面的组装方法。首先个简短的概述了为何条形测试随着实际条形测试仪器的研究情况正变得更加流行的原因,对类似的条形及基板结构、密度和几何形状等组装特性进行了讨论,强调了它们对一些不同器件类型,封装和组装特性最终测试效果的影响。     

SoC嵌入式flash存储器的内建自测试设计

深亚微米技术背景下，嵌入式存储器在片上系统芯片(system-on-a-chip，SoC)中占有越来越多的芯片面积．嵌入式存储器的测试正面临诸多新的挑战。本文论述了两种适合SoC芯片中嵌入式flash存储器的内建自测试设计方案。详细讨论了专用硬件方式内建自测试的设计及其实现，并且提出了一种新型的软硬协同方式的内建自测试设计。这种新型的测试方案目标在于结合专用硬件方式内建自测试方案并有效利用SoC芯片上现有的资源，以保证满足测试过程中的功耗限制，同时在测试时间和芯片面积占用及性能之间寻求平衡。最后对两种方案的优缺点进行了分析对比。     

一款SoC的功能测试系统的设计

针对一款基于ARM7TDMI处理器核的SoC(片上系统),设计了一个经济实用的功能测试系统,该系统采用宿主机/目标机结构.文中分析了该系统的Host程序和Monitor程序,然后以片外存储器接口模块测试、片上eSRAM(增强型SRAM)模块测试和USB客户端控制器模块测试为例,介绍SoC片上模块的测试方法.该系统符合模块化的构建思想,对于设计其他SoC功能测试系统具有一定的借鉴作用.