实现测试复用的SOC设计中的测试结构

在系统芯片SOC(system on a chip)设计中实现IP核测试复用的芯片测试结构一般包含两个部分：1)用于传送测试激励和测试响应的片上测试访问机制TAM;2)实现测试控制的芯片测试控制器。文章分析了基于测试总线的芯片测试结构,详细阐述了SOC设计中测试调度的概念,给出了一种能够灵活实现各种测试调度结果的芯片测试控制器的设计。     

一种片上网络路由器的测试方法

本文在总结片上网络多播测试方法的基础上,针对多播测试方法的缺陷提出了两种改进的片上网络路由器的测试方法。实验证明,这两种改进的方法较多播测试方法减少了测试时间和测试包数,且随着芯片规模的增大,这种优势越明显。在两种改进的方法中,方法2比方法1所需的测试时间更少。     

片上网络核心芯片的验证与测试

为提高芯片验证与测试的可靠性,针对片上网络核心芯片的结构特点,设计出一种基于宿主机/目标机通信模式的测试系统.重点描述了测试系统软硬件的设计与实现,并采用Stratix系列FPGA芯片进行原型测试和验证.实验结果表明,该系统可对芯片的复位、实现功能及稳定性进行全面测试,而且原理简单、操作方便、运行稳定,极大地提高了芯片...     

SOC芯片并行测试中几个值得关注的问题

介绍了提高测试效率的SOC芯片在片测试的两种并行测试方法,结合上海集成电路技术与产业促进中心的多个实际的SOC芯片测试项目中所积累的成功经验,针对多工位测试和多测试项目平行测试这两种并行测试方法,主要阐述了在SOC芯片的并行测试中经常遇到的影响测试系统和测试方法的问题,提出了在SOC芯片在片测试中的直流参数测试、功能测试、模数/数模转换器(ADC/DAC)测试的影响因素和解决方案,并对SOC芯片在测试过程中经常遇到的干扰因素进行分析,尽可能保证SOC芯片在片测试获得的各项性能参数精确、可靠.     

三维片上网络内核测试

片上网络是一种新兴的大规模集成电路的设计方法.片上网络的测试包括对内核、路由器和通信通道的测试.本文主要提出了一种新的片上网络内核测试方法.该方法通过重用片上网络通信结构,采用基于单播的多播数据传递方式,以及一种无死锁的完全自适应路由方法来传递测试数据,显著地提高了通信效率,提升了测试的并行性,降低了测试成本.     

基于扫描的VLSI全速测试方法

当工艺进入到超深亚微米以下,传统的故障模型不再适用,必须对电路传输延迟引发的故障采用延迟故障模型进行全速测试.给出了常用的延迟故障模型,介绍了一种基于扫描的全速测试方法,并给出了全速测试中片上时钟控制器的电路实现方案.对芯片进行测试,可以直接利用片内锁相环电路输出的高速时钟对电路施加激励和捕获响应,而测试向量的扫描输入和响应扫描输出则可以采用测试机提供的低速时钟,从而降低了全速测试对测试机时钟频率的要求.最后,对于全速测试方案提出了若干建议.     

基于PC机的智能型数字集成电路测试卡

文章介绍了一种基于ＰＣ机的智能型数字集成电路测试卡，该卡能够测试数字集成芯片的逻辑功能，自动检测未知芯片的型号及对芯片进行老化试验等。本文介绍了该测试卡的工作原理、硬件结构和软件设计方法。     

无线通讯芯片的RF测试在T2000上的实现方法

随着无线通讯技术的普及和发展,无线通讯芯片的需求量正在不断增长。无线通讯芯片的测试越来越重要。而RF测试是无线通讯芯片中关键的测试,本文基于本公司的射频SOC收发机芯片,详细介绍了无线通信芯片的RF测试在T2000上的实现方法。     

基于AVB的车载千兆以太网交换机设计

设计一种基于360环视系统的车载千兆以太网交换机,该交换机支持AVB协议。介绍选用的交换机芯片和PHY芯片的性能特点,描述交换机的框架搭建和主要模块电路的设计。交换机设计采用2片88Q5050交换芯片和3片88Q2112物理层芯片为千兆网模块进行音视频数据传输。对搭建的环境进行测试验证,测试结果满足带宽要求。设计特点为搭载了市场上第一款汽车级1000BASE-T1以太网PHY芯片88Q2112。     

TD-LTE测试终端现状及性能对比方法

在LTE发展初期,不同芯片、不同厂商的终端性能表现不一,性能差异会对网络优化问题定位造成影响。针对上述问题,介绍了TD-LTE测试终端的发展现状和测试方法,并提出了多终端对比测试方法,通过实际案例说明了终端差异对网络测试分析的影响。     

Network-on-Chip design and synthesis outlook

With the growing complexity in consumer embedded products, new tendencies forecast heterogeneous Multi-Processor Systems-On-Chip (MPSoCs) consisting of complex integrated components communicating with each other at very high-speed rates. Intercommunication requirements of MPSoCs made of hundreds of cores will not be feasible using a single shared bus or a hierarchy of buses due to their poor scalability with system size, their shared bandwidth between all the attached cores and the energy efficiency requirements of final products.

To overcome these problems of scalability and complexity, Networks-On-Chip (NoCs) have been proposed as a promising replacement to eliminate many of the overheads of buses and MPSoCs connected by means of general-purpose communication architectures. However, the development of application-specific NoCs for MPSoCs is a complex engineering process that involves the definition of suitable protocols and topologies of switches, and which demands adequate design flows to minimize design time and effort. In fact, the development of suitable high-level design and synthesis tools for NoC-based interconnects is a key element to benefit from NoC-based interconnect design in nanometer-scale CMOS technologies.

In this article we overview the benefits of state-of-the-art NoCs using a complete NoC synthesis flow, and a detailed scalability analysis of different NoC implementations for the latest nanometer-scale technology nodes. We present NoC-based solutions for the on-chip interconnects of MPSoCs that illustrate the benefits of competitive application-specific NoCs with respect to more regular NoC topologies regarding performance, area and power. Moreover, we show that it is currently feasible to synthesize in an automatic way a complete custom NoC interconnect from a high-level specification in few hours. Finally, we summarize future research challenges in the area of NoC interconnect design automation.     

Energy-Aware and Reliability-Aware Mapping for NoC-Based Architectures

Extensive research has been conducted on task scheduling and mapping on a multi-processor system on chip. The mapping strategy on a network on chip (NoC) has a huge effect on the communication energy and performance. This paper proposes an efficient core mapping for NoC-based architectures. Which focus on energy- aware and reliability-aware mapping issues for NoC-based architectures and considers new applications with insignificant inter-processor communication overhead to be added to the system. This methodology was assessed by applying it to various benchmark applications. Simulation results reveal that the proposed mapping algorithm greatly improves the reliability of the system and reduce the communication energy.     

Communication-aware VFI partitioning for GALS-based networks-on-chip

The voltage/frequency island (VFI) design paradigm is a practical architecture for energy-efficient networks-on-chip (NoC) systems. In VFI-based NoC systems, each island can be operated with different voltage and clock frequency and thus it is important to carefully partition processing elements (PEs) into islands based on their workloads and communications. In this paper, we propose an energy-efficient design scheme that optimizes energy consumption and hardware costs in VFI-based NoC systems. Since on-chip networks take up a substantial portion of system power budget in NoC-based systems, the proposed scheme uses communication-aware VFI partitioning and tile mapping/routing algorithms to minimize the inter-VFI communications. Experimental results show that the proposed design technique can reduce communication energy consumption by 32–51% over existing techniques and total energy consumption by 3–14%.     

Thermal-aware test scheduling using network-on-chip under multiple clock rates

The increasing trend in the number of cores on a single chip has led to scalability and bandwidth issues in bus-based communication. Network-on-chip (NoC) techniques have emerged as a solution that provides a much needed flexibility and scalability in the era of multi-cores. This article presents an optimal integer linear programming (ILP) formulation and a simulated annealing (SA) solution to thermal and power-aware test scheduling of cores in an NoC-based SoC using multiple clock rates. The methods have been implemented and results on various benchmarks are presented.     

基于云进化算法的NoC测试端口优化选择方法

针对片上网络(NoC)中大量节点的测试难题,提出了一种结合二维云进化算法优化选取NoC中测试端口位置,提高测试效率的方法。该方法结合NoC网格结构特点,采用重用测试访问机制和XY路由方式,由测试功耗限制确定端口对数,通过二维云模型对端口坐标进行统一建模,云进化算法自适应控制遗传变异的程度和搜索空间的范围,在测试功耗约束条件下,优化选取最佳测试端口的位置,达到总测试时间最少的目的。以SoCIN结构电路为仿真平台,分别对4×4网格和8×8网格结构NoC进行了实验仿真,结果表明,在NoC节点测试问题上,云进化算法能快速收敛到最优解,有效提高整体测试效率。     

基于BIST的NoC系统通信链路测试研究

采用内建自测试技术,完成了对NoC系统通信链路的测试。测试内容包括路由节点与其之间链路的测试,以及其与资源节点之间链路的测试。文中用硬件描述语言Verilog HDL完成各个测试模块的设计,用Quartus II软件自带的逻辑分析仪在基于FPGA的NoC系统硬件平台上完成测试。该测试方法不仅提高了故障覆盖率,还大幅降低了测试时间。     

基于遗传算法的NoC互连测试研究

针对互连测试难题的分析,提出一种基于遗传算法的NoC互连测试方案。该方案采用NoC重用测试机制的方法,在功耗限制条件下,选取合适的测试端口和最短测试路径,同时根据互连测试中实际存在的问题,对算法进行适当改进,建立基于遗传算法的NoC互连测试模型,旨在获取最优矢量集的同时,测试代价更小。当NoC的规模达到一定程度时,采用划分测试方法,缩短测试路径,降低测试时间,提高测试效率。以SoCIN结构电路为仿真平台,分别对不同规模的NoC进行实验仿真。实验结果表明,遗传算法能快速有效地收敛到最优解,在测试运行代数及测试生成时间上取得了良好的测试效果。     

Test Scheduling of NoC‐Based SoCs Using Multiple Test Clocks

Network‐on‐chip (NoC) is an emerging design paradigm intended to cope with future systems‐on‐chips (SoCs) containing numerous built‐in cores. Since NoCs have some outstanding features regarding design complexity, timing, scalability, power dissipation and so on, widespread interest in this novel paradigm is likely to grow. The test strategy is a significant factor in the practicality and feasibility of NoC‐based SoCs. Among the existing test issues for NoC‐based SoCs, test access mechanism architecture and test scheduling particularly dominate the overall test performance. In this paper, we propose an efficient NoC‐based SoC test scheduling algorithm based on a rectangle packing approach used for current SoC tests. In order to adopt the rectangle packing solution, we designed specific methods and configurations for testing NoC‐based SoCs, such as test packet routing, test pattern generation, and absorption. Furthermore, we extended and improved the proposed algorithm using multiple test clocks. Experimental results using some ITC’02 benchmark circuits show that the proposed algorithm can reduce the overall test time by up to 55%, and 20% on average compared with previous works. In addition, the computation time of the algorithm is less than one second in most cases. Consequently, we expect the proposed scheduling algorithm to be a promising and competitive method for testing NoC‐based SoCs.     

Test Scheduling for Network-on-Chip Using XY-Direction Connected Subgraph Partition and Multiple Test Clocks

It is attractive to reuse the on-chip functional interconnects as test access mechanism (TAM) in network-on-chip (NoC) system testing. However, in the methodology of NoC-reuse as TAM, the influence factors in NoC testing significantly increased. To further reduce test time and show significant gains over other work, we propose XY-direction connected subgraph partition (XYCSP) approach to eliminate the path conflicts before testing, and concurrently determine the position of test access points. We then present a multiple test clock strategy to bridge the gap between the NoC channel bandwidth and the core test wrapper bandwidth. With the help of adaptive probability gate quantum-inspired evolutionary algorithm (APGQEA) strategy, which blends adaptive strategy and multi-nary oriented techniques, the proposed NoC test scheduling algorithm permits quick exploration and exploitation of the solution space. Moreover, power constraints are also taken into account. Experimental results for the ITC’02 benchmarks show that the proposed scheme can achieve shorter test time compared to prior works.