应用于红外大面阵数据传输的接口电路设计

红外大面阵(2560×2048)数字读出电路对芯片数据接口有高速、低功耗、强驱动能力的需求。采用0.18■m互补金属氧化物半导体(Complementary Metal Oxide Semiconductor, CMOS)工艺设计了4∶1并串转换电路、电平转换电路以及采用预加重技术的低压差分信号(Low Voltage Differential Signal, LVDS)驱动器电路。并串转换电路采用双沿采样的树形结构降低时钟频率,电平转换电路采用正反馈结构提升速度,LVDS驱动电路采用可编程电流大小的预加重副通路对主通路进行高频分量补偿,以保证驱动能力和提升高速信号的完整性。接口的数据传输速率可达到1 Gbit/s。当负载电容为2 pF时,一个通道的功耗为15.8 mW@1 Gbit/s;当负载电容为8 pF且打开预加重时,一个通道的功耗为19 mW@1Gbit/s,输出电压摆幅为350 mV,输出共模电平为1.21 V,LVDS驱动电路的所有参数均满足标准协议。     

一种具有预驱动电路的低抖动LVDS驱动器

传统LVDS驱动器由于电源不稳定、驱动器与传输线之间阻抗不匹配等不良因素的影响,输出波形会出现抖动,质量下降.在传统LVDS驱动器的基础上,设计了一种新颖的LVDS驱动电路.该电路采用预驱动技术,控制输出电压的翻转和减少总输入电容,输出波形较为平滑.采用0.18μm工艺对电路进行仿真.结果显示,电路输出波形摆幅为0.345 V,输出共模电压为1.17V,总输入电容为72 fF.     

一种应用于软件定义互连系统的多协议SerDes电路

为满足片上系统的柔性互连,提出一种应用于软件定义互连系统的1.0625～10.3125Gbps多协议Ser-Des电路结构.该电路采用统一架构实现不同协议的规范需求,通过一种1×QPLL+4×Lane PLL的时钟结构实现宽频点和低抖动的时钟输出,通过可编程的发送端前向反馈均衡器和接收端线性均衡器和判决反馈均衡器电路,实现最大32dB的插损补偿.测试结果表明,所设计的SerDes电路在10.3125Gbps速率下发送总抖动为21.2ps,随机抖动均方根值为633.7fs,最大功耗29.33mW/Gbps,发送端眼图和接收端抖动容限及误码率均能够满足FC-PI-4,RapidIO 3.0,10GBase-KR,1000Base-X的协议规范要求.     

0.5μm CMOS 622Mb·s~(-1) LVDS驱动器芯片设计

文中采用0.5μm CMOS工艺设计并实现了LVDS驱动电路,整个电路由单端输入-差分输出转换电路、偏置电路、驱动输出电路和共模反馈电路组成。该电路芯片面积仅为0.47mm×0.35mm,测试结果表明,采用5V电源供电时直流功耗为30mW,输出电压摆幅及输出共模电平都满足TIA/EIA-644-A标准,电路最高工作速率高于622Mb·s~(-1),可以应用于LVDS传输系统。     

一种高速LVDS驱动电路的设计

介绍了一种采用0.18μm CMOS工艺制作的高速(500MHz)LVDS驱动电路.分析了开关时序和共模反馈对电路的影响,采用开关控制信号整形电路和基于"主-从"结构的共模设置电路,得到适当的开关时序和较好的共模电平设置,使LVDS输出电路具有更小的过冲电压和更稳定的共模电平.该LVDS驱动电路用于1GHz 14位高速D/A转换器芯片.样品电路测试结果表明,输出速率在500MHz时,LVDS驱动电路的指标满足IEEE-1596 reduced range link标准.     

一种深低温环境LVDS驱动电路

研究了深低温环境下MOS管与LVDS驱动电路的工作特性。与常温环境相比,LVDS电路在77 K环境下的输出电流更大,导致输出差分信号幅值增大。MOS管在77 K低温环境下的载流子迁移率为常温下的3倍,导致器件电流增大。根据低温条件下器件变化特性的数据分析结果,调节电路结构与器件参数,设置多档可调参考电流,并调节LVDS输出信号于标准范围内。采用标准0.35 μm CMOS工艺进行流片验证。结果表明,LVDS驱动电路在77 K环境下工作时,共模电平为1.2 V,电压摆幅为400 mV。     

一种高性能LVDS收发器的设计

基于0.18μm SiGe BiCMOS工艺,设计了一种用于10位200 MHz高速流水线模数转换器的CMOS LVDS收发电路。该收发电路由发射器(TX)和接收器(RX)组成。发射器通过带共模反馈的闭环控制电路,将0~3.3 V的CMOS信号转换成(1.2±0.35)V的LVDS信号。接收器采用一个轨至轨预运算放大器保证LVDS信号的完整接收,并实现一定的增益,之后由迟滞比较器和输出缓冲器实现对共模噪声的抑制以及信号驱动能力的提高,最终正确恢复出CMOS信号。仿真结果表明,在400 MHz脉冲输入下,收发器可以稳定工作在3.3 V电源电压,总功耗仅为22.4 mW。     

一种带电平转换功能的双电源电压输出电路

出于性能、功耗和兼容性的考虑,芯片的核心电路与I/O电路一般采用不同的电源电压.文中设计了一种新型2.5V/5V双电源电压输出电路,此电路带有新型电平转换电路,能够将摆幅为0～2.5V的内部信号转换为摆幅为0～5V的输出信号.同时,文中所设计的输出电路只使用2.5V耐压的薄栅氧MOS器件,虽然在5V电压下工作,却没有栅氧过压问题.     

低电压低功耗CMOS电流反馈运算放大器的设计

设计了一种低压低功耗的电流反馈运算放大器(CFOA),采用了0.18μm CMOS工艺,工作在0.9 V的电源电压下,并给出了Spectre仿真结果,功耗为245μW。输入采用了轨对轨的结构以提高输入电压摆幅,输出采用互补输出结构,使输出工作在甲乙类状态,以降低电路的功耗。     

基于标准CMOS工艺的一款宽带限幅放大器芯片设计

采用SMIC 0．35μm CMOS混合信号工艺来设计开发一款适用于SDH STM-16的光接收机前端限幅放大器芯片。该限幅放大器的设计采用了电容中和技术来实现带宽的扩展,可满足2．5Gbps速率要求,芯片电路拥有信号丢失检测和自动静噪功能。芯片版图的参数提取仿真表明：芯片最小输入动态范围可达2mV,50Ω负载上的双端输出摆幅约为1400mVpp在3．3V供电下静态功耗仅为66mW,动态功耗为105mW,有实际推广价值。     

Design of high speed LVDS transceiver ICs

The design of low-power LVDS(low voltage differential signaling) transceiver ICs is presented.The LVDS transmitter integrates a common-mode feedback control on chip,while a specially designed pre-charge circuit is proposed to improve the speed of the circuit,making the highest data rate up to 622 Mb/s.For the LVDS receiver design, the performance degradation issues are solved when handling the large input common mode voltages of the conventional LVDS receivers.In addition,the LVDS receiver also supports ...     

一个0.18μm高速低功耗的发送和接收电路

提出了一种高速低功耗的低压差分接口电路,它可以应用于CPU,LCD,FPGA等需要高速接口的芯片中.在发送端,一个稳定的参考电压和共模反馈电路被应用于低压差分电路中,它使得发送端能够克服电源、温度以及工艺引起的波形变化.在接收端采用了轨到轨的放大器结构,它町以工作到1.6Gb/s.芯片设计加工采用的是0.18μm CMOS工艺,芯片测试结果表明,整个发送接收端数据传输速率可以达到1.6Gb/s,同时发送和接收端的功耗分别是35和6mW.     

Design and realization of 1.3?Gb/s off-chip transmission circuitry using 0.35?μm CMOS technology

Low-voltage-differential-signaling (LVDS) is one of the very popular technologies which simultaneously addresses low dynamic power consumption and high data rate transmission in modern high speed circuit applications. In this paper, system level integration design approach is applied to design LVDS transmitter featuring high off-chip data rate. Full wave electromagnetic simulation technique was adopted to accurately characterize possible couplings and parasitic effects induced from the off-chip components which then acted as the termination of the output circuitry. Common mode feedback was included to perform fine tuning on the offset leading to much higher overall precision. Meanwhile, generation of the controlled current and voltage across termination was guaranteed through the introduction of a constant transconductance bias network. The design was implemented using TSMC 3.3?V 0.35???m CMOS technology with overall chip size of 0.923?mm². At a DC power consumption level of 29.4?mW, the LVDS transmitter exhibited an off-chip data rate of 1.3?Gb/s validated through measurements.     

LVDS I/O interface for Gb/s-per-pin operation in 0.35-μm CMOS

This paper presents the design and the implementation of input/output (I/O) interface circuits for Gb/s-per-pin operation, fully compatible with low-voltage differential signaling (LVDS) standard. Due to the differential transmission technique and the low voltage swing, LVDS allows high transmission speeds and low power consumption at the same time. In the proposed transmitter, the required tolerance on the dc output levels was achieved over process, temperature, and supply voltage variations with neither external components nor trimming procedures, by means of a closed-loop control circuit and an internal voltage reference. The proposed receiver implements a dual-gain-stage folded-cascode architecture which allows a 1.2-Gb/s transmission speed with the minimum common-mode and differential voltage at the input. The circuits were implemented in a 3.3-V 0.35-μm CMOS technology in a couple of test chips. Transmission operations up to 1.2 Gb/s with random data patterns and up to 2 Gb/s in asynchronous mode were demonstrated. The transmitter and receiver pad cells exhibit a power consumption of 43 and 33 mW, respectively     

一个0.18μm高速低功耗的发送和接收电路

提出了一种高速低功耗的低压差分接口电路,它可以应用于CPU,LCD,FPGA等需要高速接口的芯片中.在发送端,一个稳定的参考电压和共模反馈电路被应用于低压差分电路中,它使得发送端能够克服电源、温度以及工艺引起的波形变化.在接收端采用了轨到轨的放大器结构,它町以工作到1.6Gb/s.芯片设计加工采用的是0.18μm CMOS工艺,芯片测试结果表明,整个发送接收端数据传输速率可以达到1.6Gb/s,同时发送和接收端的功耗分别是35和6mW.     

一种6.25 Gb/s带预加重结构的低压差分发送器

采用SMIC 40 nm CMOS工艺,设计了一种带预加重结构的低压差分(LVDS)发送器。低压差分驱动器采用双运放反馈控制电路,可稳定输出信号的摆幅。采用边沿检测电流注入的预加重电路,对输出进行高频预加重,克服了数据高速传输中高频信号的损失。该发送器的速率为6.25 Gb/s,输出差分信号摆幅为300 mV,预加重比例为3.5 dB,功耗为7.1 mW。该低压差分发送器可应用于高速IO物理层电路中。     

A 6 Gbps/pin Low‐Power Half‐Duplex Active Cross‐Coupled LVDS Transceiver with Switched Termination

A novel linear switched termination active cross‐coupled low‐voltage differential signaling (LVDS) transceiver operating at 1.5 GHz clock frequency is presented. On the transmitter side, an active cross‐coupled linear output driver and a switched termination scheme are applied to achieve high speed with low current. On the receiver side, a shared preamplifier scheme is employed to reduce power consumption. The proposed LVDS transceiver implemented in an 80 nm CMOS process is successfully demonstrated to provide a data rate of 6 Gbps/pin, an output data window of 147 ps peak‐to‐peak, and a data swing of 196 mV. The power consumption is measured to be 4.2 mW/pin at 1.2 V.     

一种高速低功耗LVDS发射器设计

依据标准IEEE Std.1596.3-1996,提出了一种高速低电压差分信号(LVDS)发射器电路,给出电路结构、仿真数据及版图。电路采用65 nm 1P9M CMOS Logic工艺设计实现。用Spectre仿真器对发送器进行模拟仿真,仿真结果表明该发射器电路在电源电压为2.5 V的工作条件下,数据传输速率可以达到2 Gbps,平均功耗为9mW。     

Equalization and pre-emphasis based LVDS transceiver

This work presents an area-efficient, low-power, high data rate low voltage differential signal (LVDS) transmitter and receiver with signal quality enhancing techniques. The proposed common mode feedback scheme significantly reduces the size of the LVDS transmitter by eliminating the use of area consuming passive resistor and capacitor used for close loop stability compensation. A preemphasis technique has been introduced to enhance the transmitter output’s signal quality without significantly increasing the power draw. On the receiver part, an equalization technique has also been introduced to further enhance signal quality, increases data rate and improved jitter with relatively low power consumption. The LVDS transmitter consumes 5.4 mA of current while driving an external 100 ohm resistor with an output voltage swing of 440 mV. The chip consumes an area of 0.044 mm². This LVDS receiver has an input common mode range from 0.1 to 1.6 V. It consumes 34 mW of power with a maximum data rate of 2 Gbps. It consumes an area of 0.147 mm² a jitter of 11.74 ps rms. A test chip is implemented using 0.18 μm CMOS process.     

Low-power LVDS I/O interface for above 2Gb/s-per-pin operation

Low Voltage Differential Signaling (LVDS) has become a popular choice for high-speed serial links to conquer the bandwidth bottleneck of intra-chip data transmission. This paper presents the design and the implementation of LVDS Input/Output (I/O) interface circuits in a standard 0.18 μm CMOS technology using thick gate oxide devices (3.3 V), fully compatible with LVDS standard. In the proposed transmitter, a novel Common-Mode FeedBack (CMFB)circuit is utilized to keep the common-mode output voltage stable ...