浅析模拟与混合信号电路测试与故障检测方法

模拟和混合信号电路本身具有相当高的复杂性及专业性,使得模拟和混合信号电路测试与故障检测无法在传统数字电路测试方法下得到满足。文章通过介绍模拟和混合信号电路测试与故障检测的研究现状,分析了模拟与混合信号电路的测试与故障检测方法,并在传统测试技术的基础上研究了新的诊断方法,具有参考价值。     

低功耗测试序列生成电路的建模及分析

为了解决深亚微米、SOC和低功耗电路中的测试问题,低功耗测试序列RSIC序列的生成方法得以研究和发展.文章提出关于RSIC序列生成电路的建模和分析理论.其研究特色是抽象出此类复杂电路固有特性的通用模型,建立一套简洁、准确的数学描述和分析方法,论证了此类电路的一系列特性,并通过片外测试的模拟结果来验证RSIC序列的低功耗.该研究结果为RSIC序列研究和应用提供了强有力的理论基础和分析方法.     

数控直流稳压电源的测试

文章分部分介绍了在单片机控制下的数控直流稳压电源的测试,针对不同的电路特点,采用了不同的测试方法,同时分析了数字技术和模拟技术相互转换的概念.通过巧妙的软件设计和简易的硬件电路,实现单片机控制.该设计能方便、灵活和准确地产生的所需要的电压,通过测试能达到预期效果.     

扫描电路测试功耗综述

随着集成电路制造技术的发展.高集成度使得测试时的功耗成为集成电路设计必须考虑的一个重要因素,低功耗测试也就成为了测试领域一个令人关注的热点.目前,低功耗测试技术的研究还在发展之中,工业生产中低功耗测试方法还没有得到充分的应用.在集成电路中采用扫描结构的可测试性设计方法,能够提高测试覆盖率.缩短测试时间,已在集成电路测试中得到大量应用.基于扫描结构的数字集成电路,学术界已提出了许多方法降低该电路的测试功耗,本文对此方面的研究进行综述.随着测试技术的发展,测试功耗的理论也将日益深入.     

微波功率器件的扇形线测试电路

在微波电路原理和半导体器件物理的基础上,设计和模拟了两种用于微波功率器件的测试电路,并且设计了与之配套的测试夹具.采用矢量网络分析仪对该测试电路和夹具在3～8GHz范围内进行了小信号测试.模拟和测试结果都表明,采用扇形线的测试电路性能较好.最后采用该电路和夹具对C波段AlGaN/GaN HEMT微波功率器件进行了微波功率测试,测试频率为5.4GHz.实验测得最大功率增益为8.75dB,最大输出功率为33.2dBm.     

伪随机测试生成在混合电路参数测试中的应用

混合信号电路在通信、多媒体等领域获得越来越广泛的应用。然而,测试也变得更复杂。传统上对模拟电路的测试采用的是直接功能测试,即直接测量电路的性能参数Z。采用该测试方法,其缺点是测试时间长、测试设备昂贵、且精度差。本文针对这一问题进行研究,详细讨论了利用伪随机技术进行混合信号电路测试的方法。     

IP硬核无损测试技术

针对大量IP硬核精准、快速的测试验证需求,在分析现有IP硬核测试技术的基础上,研究了IP硬核无损测试技术.通过设计模拟用户片上系统(SOC)的通用评估系统,将被测IP硬核嵌入在测试电路中,并引入软硬件补偿结构,对信号时序进行校准补偿,对IP硬核精确输入进行控制和监测.结合外部自动测试设备(ATE)与片上评测电路,实现对IP硬核的功能、性能以及可靠性等的精确验证.实际完成了一款基于片上评测电路的静态随机存储器(SRAM) IP硬核测试设计与验证,实现该IP硬核关键时序参数测试,以数据建立时间这一参数为例,分析了其具体测试方法并得到测试结果.采用该测试技术,IP硬核时间参数的测试精度可达ps级,相较于IP硬核封装后测试,充分体现了结果数据的精确性.     

模拟VLSI电路故障诊断的相关分析法

为了提高模拟VLSI电路的测试精度,提出了一种基于数字信号处理的模拟VLSI电路测试方法.将测试响应经余弦调制实现的数字滤波器组完成子带滤波,随后对各子带滤波序列进行能量计算和相关分析,实现模拟响应的数字特征提取.对国际标准电路中的19个故障的实验表明:子带滤波序列的能量计算适合诊断硬故障;相关分析既可诊断硬故障,又可诊断软故障.实验还表明该方法对故障的分辨率远高于文献[7].     

测试技术发展趋势

IC测试、通信测试、网络测试和 虚拟仪器的发展已出现一些新的势态。降低测试成本成为发展IC测试的首要目标对体积更小、功能更强的芯片的需求正推动IC产业的发展,同时也推动着IC设计和测试的发展。对于系统芯片（SOC）的测试,其成本已几乎占芯片成本的一半。根据英特尔公司副总裁提出的测试摩尔定律,未来几年,每一晶体管的硅投资成本将低于其测试成本。 因此未来IC测试设备制造商面临的最大挑战是如何降低测试成本。过去的集成电路主要分为模拟电路、混合信号电路和数字电路。１９９８年,称之为MACH-D的（即存储器、模拟、通…     

低功耗测试矢量生成技术的研究

在集成电路内建自测试的过程中,电路的测试功耗通常显著高于正常模式产生的功耗,因此低功耗内建自测试技术已成为当前的一个研究热点。为了减少被测电路内部节点的开关翻转活动率,研究了一种随机单输入跳变（Random Single Input Change,RSIC）测试向量生成器的设计方案,利用VHDL语言描述了内建自测试结构中的测试向量生成模块,进行了计算机模拟仿真并用FPGA（EP1C6Q240C8）加以硬件实现。实验结果证实了这种内建自测试原理电路的正确性和有效性。     

Test Generation for Mixed-Signal Devices Using Signal Flow Graphs

We describe a new reverse simulation approach to analog and mixed-signal circuit test generation that parallels digital test generation. We invert the analog circuit signal flow graph, reverse simulate it with good and bad machine outputs, and obtain test waveforms and component tolerances, given circuit output tolerances specified by the functional test needs of the designer. The inverted graph allows backtracing to justify analog outputs with analog input sinusoids. Mixed-signal circuits can be tested using this approach, and we present test generation results for two mixed-signal circuits and four analog circuits, one being a multiple-input, multiple-output circuit. This analog backtrace method can generate tests for second-order analog circuits and certain non-linear circuits. These cannot be handled by existing methods, which lack a fault model and a backtrace method. Our proposed method also defines the necessary tolerances on circuit structural components, in order to keep the output circuit signal within the envelope specified by the designer. This avoids the problem of overspecifying analog circuit component tolerances, and reduces cost. We prove that our parametric fault tests also detect all catastrophic faults. Unlike prior methods, ours is a structural, rather than functional, analog test generation method.     

Testing analog circuits using spectral analysis

In this work a test strategy for analog circuits based on spectral analysis is proposed. The test strategy is blind, in the sense that only statistical information about the input signal is needed, but no sampling of the input signal is required. This feature allows the test of analog circuits with minimum analog hardware addition. In the context of Systems-on-Chip, this strategy needs only the inclusion of a small random signal generator, and transfers most of the signal processing to the digital domain, allowing the use of a purely digital tester or a digital BIST technique. This paper presents the underlying principle of the method and experimental test results for linear analog systems.     

Test generation for specification test of analog circuits using efficient test response observation methods

In this paper, a new automated test generation methodology for specification testing of analog circuits using test point selection and efficient analog test response waveform capture methods for enhancing the test accuracy is proposed. The proposed approach co-optimizes the construction of a multi-tone sinusoidal test stimulus and the selection of the best set of test response observation points. For embedded analog circuits, it uses a subsampling-based digitization method compatible with IEEE 1149.1 to accurately digitize the analog test response waveforms. The proposed specification approach uses ‘alternate test’ framework, in which the specifications of the analog circuit-under-test are computed (predicted) using statistical regression models that are constructed based on process variations and corresponding variations of test responses captured from different test observation points. The test generation process and the test point selection process aim to maximize the accuracy of specification prediction. Experimental results validating the proposed specification test approach are presented.     

Synthesis method for testable electrical networks using 1st order building blocks

This work presents a method for synthesizing testable continuous-time linear time-invariant electrical networks using 1st order blocks for the implementation of analog linear circuits. A functional-structural fault model for the block, and a fault dictionary are proposed together with a simple set of test vectors. The method allows, also, the fault grade evaluation for the modeled faults. The results obtained from the two application examples have shown the suitability of the approach as a design for test method for analog circuits.     

Automated System-Level Test Development for Mixed-Signal Circuits

While in the digital domain, test development is primarily conducted with the use of automated tools, knowledge-based, ad hoc test methods have been in use in the analog domain. High levels of design integration and increasing complexity of analog blocks within a system necessitate automated system-level analog test development tools. We outline a methodology for specification-based automated test generation and fault simulation for analog circuits. Test generation is targeted at providing the highest coverage for each specified parameter. The flexibility of assigning analog test attributes is utilized for merging tests leading to test time reduction with no loss in test coverage. Further optimization in test time is obtained through fault simulations by selecting tests that provide adequate coverage in terms of several components and dropping the ones that do not provide additional coverage. A system-level test set target in the given set of specifications, along with fault and yield coverages in terms of each targeted parameter, and testability problems are determined through the proposed methodology.     

Statistical Tolerance Analysis for Assured Analog Test Coverage

Increasing numbers of analog components in today's systems necessitate system level test composition methods that utilize on-chip capabilities rather than solely relying on costly DFT approaches. We outline a tolerance analysis methodology for test signal propagation to be utilized in hierarchical test generation for analog circuits. A detailed justification of this proposed novel tolerance analysis methodology is undertaken by comparing our results with detailed SPICE Monte-Carlo simulation data on several combinations of analog modules. The results of our experiments confirm the high accuracy and efficiency of the proposed tolerance analysis methodology.     

Fault simulation of linear analog circuits

Research in the areas of analog circuit fault simulation and test generation has not achieved the same degree of success as its digital counterpart owing to the difficulty in modeling the more complex analog behavior. This article presents a novel approach to this problem by mapping the good and faulty circuits to thediscrete Z-domain. An efficient fault simulation is then performed on this discretized circuit for the given input test wave form. This simulator provides an order of magnitude speedup over traditional circuit simulators. An efficient fault simulator and the formulation of analog fault models opens up the ground for analog automatic test generation.     

Unified built-in self-test for fully differential analog circuits

The reduction of test costs, especially in high safety systems, requires that the same test strategy is employed for design validation, manufacturing and maintenance tests, and concurrent error detection. This unification of off-line and on-line tests has already been attempted for digital circuits and it offers the advantage of serving to all phases of a system lifetime.Market pressure originating from the high costs of analog and mixed signal testing has resulted in renewed efforts for the test of analog parts. In this paper, off-line and on-line test techniques for fully differential analog circuits are presented within an unified approach. The high performance of these circuits makes them very popular for many applications, including high safety, low voltage and high speed systems.A test master compliant with IEEE Std. 1149.1 is described. The Analog Unified BIST (AUBIST) is exemplified for linear and non-linear switched-capacitor circuits. High fault coverage is achieved during concurrent/on-line testing. An off-line test ensures the goal of self-checking circuits and allows the diagnosis of faulty parts. The self-test of the AUBIST circuitry is also considered.This work is part of AMATIST ESPRIT-III Basic Research Project, funded by CEC under contract #8820.     

数模混合电路故障诊断方法的研究

随着电子技术的迅猛发展,电路系统的复杂程度急剧增加,越来越多的电路同时包含了数字信号和模拟信号,使得电路系统的测试难度越来越大,电路测试也因此面临着更大的挑战。目前的电路故障方法主要还是针对数字电路和模拟电路的,但是数模混合电路的测试仍然是一个很年轻的领域。针对目前数模混合电路测试的现状,对其故障诊断的各种方法的基本思想进行介绍。重点介绍基于DES理论的数模混合电路故障诊断。     

Optimization-based multifrequency test generation for analog circuits

A robust test set for analog circuits has to detect faults under maximal masking effects due to variations of circuit parameters in their tolerance box. In this paper we propose an optimization based multifrequency test generation method for detecting parametric faults in linear analog circuits. Given a set of performances and a frequency range, our approach selects the test frequencies that maximize the observability on a circuit performance of a parameter deviation under the worst masking effects of normal variations of the other parameters. Experimental results are provided and validated by HSpice simulations to illustrate the proposed approach.