Test Generation for Mixed-Signal Devices Using Signal Flow Graphs

We describe a new reverse simulation approach to analog and mixed-signal circuit test generation that parallels digital test generation. We invert the analog circuit signal flow graph, reverse simulate it with good and bad machine outputs, and obtain test waveforms and component tolerances, given circuit output tolerances specified by the functional test needs of the designer. The inverted graph allows backtracing to justify analog outputs with analog input sinusoids. Mixed-signal circuits can be tested using this approach, and we present test generation results for two mixed-signal circuits and four analog circuits, one being a multiple-input, multiple-output circuit. This analog backtrace method can generate tests for second-order analog circuits and certain non-linear circuits. These cannot be handled by existing methods, which lack a fault model and a backtrace method. Our proposed method also defines the necessary tolerances on circuit structural components, in order to keep the output circuit signal within the envelope specified by the designer. This avoids the problem of overspecifying analog circuit component tolerances, and reduces cost. We prove that our parametric fault tests also detect all catastrophic faults. Unlike prior methods, ours is a structural, rather than functional, analog test generation method.     

A Level-Crossing Approach for the Analysis of RF Modulated Signals Using Only Digital Test Resources

The test of analog & RF circuits at wafer-level suffers from both quality and throughput limitations, especially due to probing issues and limited count of expensive instrumentation resources. Since final test after packaging guarantees product performances, constraints on wafer-level test can be relaxed. This paper investigates a signal acquisition protocol based on the use of digital tester channels to perform the demodulation of analog/RF signals. Due to the large availability of such hardware resources on most testers, this approach allows to setup a multi-site strategy, thus increasing the test throughput. The fundamental concept is to capture the signal through the 1-bit comparator available in a digital tester channel and to process the resulting bit stream to retrieve the analog/RF signal characteristics. In this paper, the proposed solution is illustrated for the demodulation of Frequency-Modulated (FM) and Amplitude-Modulated (AM) signals. Both simulation and experimental results obtained with a Verigy 93K platform are presented.     

A Statistical Sampler for a New On-Line Analog Test Method

This work shows a new strategy to the on-line test of analog circuits. The technique presents a very low analog overhead and it is completely digital. In the System-on-Chip (SoC) environment the on-line test can be developed by using processing power already available in the system. As all the signal processing is done in the digital domain, it allows use of a purely digital tester or a digital BIST technique. The main principle of operation is based on the observation of statistical properties of the circuit under test. Since it has low analog power and performance overhead, the proposed technique can be used to analyze the output of several stages of complex analog systems without the use of switches or analog multiplexors for reconfiguration, and no additional AD converter is needed. This paper presents the fundamentals of the proposed test method and some experimental results illustrating the operation of the Statistical Sampler concerning linear analog systems.     

Test generation algorithm for analog systems based on support vector machine

In some methods for test generation, an analog device under test (DUT) is treated as a discrete-time digital system by placing it between a digital-to-analog converter and an analog-to-digital converter. Then the test patterns and responses can be performed and analyzed in the digital domain. We propose a novel test generation algorithm based on a support vector machine (SVM). This method uses test patterns derived from the test generation algorithm as input stimuli, and sampled output responses of the analog DUT for classification and fault detection. The SVM is used for classification of the response space. When the responses of normal circuits are similar to those of faulty circuits (i.e., the latter have only small parametric faults), the response space is mixed and traditional algorithms have difficulty in distinguishing the two groups. However, the SVM provides an effective result. This paper also proposes an algorithm to calculate the test sequence for input stimuli using the SVM results. Numerical experiments prove that this algorithm can enhance the precision of test generation.     

Unified built-in self-test for fully differential analog circuits

The reduction of test costs, especially in high safety systems, requires that the same test strategy is employed for design validation, manufacturing and maintenance tests, and concurrent error detection. This unification of off-line and on-line tests has already been attempted for digital circuits and it offers the advantage of serving to all phases of a system lifetime.Market pressure originating from the high costs of analog and mixed signal testing has resulted in renewed efforts for the test of analog parts. In this paper, off-line and on-line test techniques for fully differential analog circuits are presented within an unified approach. The high performance of these circuits makes them very popular for many applications, including high safety, low voltage and high speed systems.A test master compliant with IEEE Std. 1149.1 is described. The Analog Unified BIST (AUBIST) is exemplified for linear and non-linear switched-capacitor circuits. High fault coverage is achieved during concurrent/on-line testing. An off-line test ensures the goal of self-checking circuits and allows the diagnosis of faulty parts. The self-test of the AUBIST circuitry is also considered.This work is part of AMATIST ESPRIT-III Basic Research Project, funded by CEC under contract #8820.     

A robust CMOS compander

A robust CMOS compander circuit meeting all of the requirements for analog cellular telephony and using an improved sigma-delta compander topology is presented. Rather than digitizing and reconstructing the input signal using a sigma-delta modulator as has been done previously, only the amplitude path is digitized while the voice path remains analog. The amplitude information is obtained digitally, and is reduced to a single bit using a first-order sigma-delta modulator. Performing this function digitally eliminates problems due to analog offsets and in implementing the long time constant required. The output signal is formed by gating the analog input signal under control of the amplitude signal. The expander and compressor circuits each consist of a single op amp and 2000 gates of digital logic, and have been implemented on 0.8-μm CMOS processes. The ADC for the amplitude path uses a compact switched-capacitor second-order sigma-delta modulator implemented using a single amplifier. No external components are required. Tracking error for the compressor was measured to be less than 0.3 dB over a 60-dB input range when operating on a 3.0-V supply. The test time, when compared to conventional compander implementations, is considerably reduced     

A Voiceband Codec with Digital Filtering

Oversampling and digital filtering have been used to design a per-channel voiceband codec with resolution that exceeds the typical transmission system requirement by more than 15 dB. This extended dynamic range will allow for the use of digital processing in the management of signal levels and system characteristics in many telecommunication applications. Digital filtering contained in the codec provides rejection of out-of-band inputs and smoothing of the analog output that is sufficient to eliminate the need for analog filtering in most telephone applications. Some analog filtering may be required only to maintain the expanded dynamic range in cases where there is a danger of large amounts of out-of-band energy on the analog input impairing the dynamic range of the modulator. The encoder portion of the oversampled codec comprises an interpolating modulator that samples at 256 kHz followed by digital filtering that produces a 16-bit PCM code at a sample rate of 8 kHz. In the decoder, digital processing is used to raise the sampling rate to 1 MHz prior to demodulation in a 17-level interpolating demodulator. The circuits in the codec are designed to be suitable for large-scale integration. Component matching tolerances required in the analog circuits are of the order of only ± 1 percent, While the digital circuits can be implemented with fewer than 5000 gates with delays on the order of 0.1 μs. In this paper the response of the codec is described mathematically and the results are confirmed by measurements of experimental breadboard models.     

A single-chip CMOS analog/digital mixed NTSC decoder

A single-chip CMOS LSI that integrates all analog-to-digital (A/D), digital-to-analog (D/A), peripheral, and digital signal processing circuits necessary for a digital National Television System Committee (NTSC) signal decoder is described. The LSI chip accepts composite NTSC video signals in analog form, digitizes them using the on-chip A/D converter, converts them to component RGB signals, and then converts the signals to analog form by using the on-chip D/A converters. The development of circuits that maximize use of the input digital data is discussed. A 6-b A/D circuit is used to reduce the circuit size. Circuits that help maintain acceptable picture quality despite 6-b resolution were developed. Besides analog NTSC signal input and RGB signal output, the IC can also input and output digital NTSC signals, Y/C (luminance, chrominance) signals, and RGB signals. Applications of the LSI are presented     

Switched-current oversampling converters

There are many choices in designing a real-time signal processing system. To exploit the advantages that inexpensive digital CMOS process technologies provide, it is usually a good choice to use digital signal processing circuits extensively and to use analog circuits only as a bridge between the real analog world and digital signal processing circuits. The mixed analog/digital circuits usually have high performance and low cost. SI oversampling converters in particular are the ideal choice as the front ends for the mixed analog/digital design. They serve to bridge the real world and modern process technologies     

频谱分析仪的数字中频设计方案

为了提高频谱分析仪的频率分辨率,同时降低模拟中频、视频电路组件的生产难度,现代频谱分析仪大多采用数字中频技术,利用模数转换器把模拟中频信号转换为数字信号,经过数字下变频、数字滤波、数字检波或快速傅里叶变换运算后得到射频信号的幅度和频率信息,再经过视频滤波处理后得到清晰的信号频谱.文中论述的信号处理方案实现了频谱的数字分析,在实际应用中验证了其指标的稳定.     

基亏DSP的多路音／视频采集处理系统设计

采用TI公司的TMS320DM642型数字媒体数字信号处理器（DSP）设计多路音／视频采集处理系统，实现实时处理4路模拟视频和音频输入、1路模拟／数字视频和1路模拟音频信号输出的功能，该系统可适应PAL／NTSC标准复合视频CVBS或分量视频Y／C格式的模拟信号和标准麦克风或立体声音频模拟输入，具有PAL／NTSC标准S端子或数字RGB模拟／数字信号输出和标准立体声音频模拟输出。并给出软／硬件设计原理和电路。     

Fault simulation of linear analog circuits

Research in the areas of analog circuit fault simulation and test generation has not achieved the same degree of success as its digital counterpart owing to the difficulty in modeling the more complex analog behavior. This article presents a novel approach to this problem by mapping the good and faulty circuits to thediscrete Z-domain. An efficient fault simulation is then performed on this discretized circuit for the given input test wave form. This simulator provides an order of magnitude speedup over traditional circuit simulators. An efficient fault simulator and the formulation of analog fault models opens up the ground for analog automatic test generation.     

一种高性能机车速度数模转换装置的设计

为了适应铁路机车运行高性能、高可靠性要求,设计了一种高性能的机车速度数模转换装置。其作用是将机车轮对上的DF16型光电速度传感器传输来的数字脉冲信号,转换成0~6 V,0~20 mA两种模拟信号。该装置仅用2块IC芯片LM331和AD694及少量外围电路。其中LM331是将输入的数字脉冲信号转换成一定幅值的电压信号,然后由AD694将输出的电压信号转换成标准0~20 mA电流和0~6 V电压两种信号输出。该装置具有转换速度快、精度高(0.1%)、温度漂移小(100 ppm/℃)性能可靠等优点,是一款高性能的数模转换装置。     

An all-band TV tuner IC with 10-GHz 100-V mixed analog/digital Sibipolar technology

An all-band TV tuner IC with an on-chip PLL and a high-voltage output stage is developed. The use of a self-aligned bipolar technology called high-voltage compatible sidewall base contact structure (HV-SICOS) allows the integration of 1-GHz analog circuits, 1-GHz low-power ECL-I²L PLL circuits, and a 0.5- to 30-V tuning diode bias current on the same chip. The analog block has a VCO and mixer pair for the VHF/CATV and another pair for the UHF bands, a UHF input amplifier, an IF amplifier, and a VCO signal switching circuit. To suppress the digital noise level for mixed analog/digital mode operation, the PLL is constructed with high-speed ECL circuits for divide-by-four and dual modulus prescalers, and low-power I²L circuits. An isolation area is placed between the analog and digital blocks. Conversion gain of 24 dB for VHF/CATV and 33 dB for UHF, a noise figure of 10 dB, and 1% cross modulation of 95 dB-μV are obtained. This IC operates with a total power dissipation of 200 mW on a 3-mm×4-mm chip     

A 1.3 GHz SOI CMOS test chip for low-power high-speed pulseprocessing

A test chip has been fabricated in a fully depleted SOI CMOS process with 0.25-μm drawn gate length, It successfully demonstrates the types of circuits required to perform digital filtering, detection, and data thinning functions at high clock speeds. The test chip contains over 5000 transistors and was clocked at speeds up to 1.3 GHz. A target application for these circuits is a very wideband compressive receiver for real-time spectral analysis, which requires digital signal processing to be performed on a 20-Gb/s data stream formed by digitizing a stream of fast analog pulses. Adjustable high-speed on-chip clocks, input and output registers, and large decoupling capacitors allowed testing of the chip to be performed using an inexpensive, low-speed probe card and a standard wafer prober     

调制混合滤波器组的宽带模拟信号采样研究

对于超宽带模拟信号,很难用单个模拟数字转换器（ADC）直接进行采样。该文提出了一种新的并行调制混合滤波器组结构用于实现超宽带模拟信号的采样,首先,将每一路宽带模拟输入信号进行余弦调制,并用相同的低通模拟滤波器均匀分割输入信号的带宽;然后,采用相同的ADC将子带信号数字化;各路子带信号通过上采样器后用数字综合滤波器综合得到原宽带模拟输入信号的数字重构。综合滤波器采用总体最小二乘准则下的特征值滤波器设计方法得到。本文所提出的系统结构不需要使用高速的采样保持电路,降低了系统实现的难度,并且设计的系统具有与其它混合滤波器组相近的重构性能。仿真结果表明了本方法的有效性。      

多通道高速ADC电路PCB设计技术浅谈

ADC是将模拟信号转换为数字信号的芯片,它在电路系统中的作用决定了它必然和其它大量数字电路一起使用,所以在其PCB设计中除了需要考虑一般PCB设计中要注意的问题之外,还要在多方面引起特别注意,尤其是在高速应用中。本文就针对多通道高速ADC电路设计的特点,以E2V公司的EV10AQ190芯片为例,重点讨论了包含多通道高速ADC的硬件电路设计中印刷电路板布局时所必须引起注意的问题,包括数字地和模拟地。数字电源和模拟电源的处理,ADC输入信号的隔离问题,采样时钟的处理和输出信号的阻抗匹配等问题。     

Measurement of digital noise in mixed-signal integrated circuits

This paper proposes a method of measuring the influence of digital noise on analog circuits using wide-band voltage comparators as noise detectors. Noise amplitude and r.m.s voltage are successfully measured by this method. A test chip is fabricated to measure the digital noise influence. From the experimental results, it is shown that the digital noise influence can be considerably reduced by using a differential configuration in analog circuits for mixed-signal IC's. The digital noise influence can be further reduced by lowering the digital supply voltage. These results show that the voltage-comparator-based measuring method is effective in measuring the influence of digital noise on analog circuits     

一种具有失配校准技术的轨到轨输入逐次逼近型模数转换器设计

传统的逐次逼近型模数转换器很难对输入等于电源电压的模拟信号进行正确的模数转换,本文提出了一种新型的逐次逼近型模数转换器,能够对输入幅度等于电源电压的输入信号进行正确的转换,并且具有用于缩短采样时间的采样保持放大器电路,同时针对比较器失调和电容阵列失配提出了校准技术,进一步提高了转换精度。测量结果显示该模数转换器的最大信噪谐波失真比可以达到72dB,有效输入信号带宽为1.25MHz,消耗功耗为1mW,相应的FOM指数为123fJ。     

Evolutionary derivation of optimal test sets for neural network based analog and mixed signal circuits fault diagnosis approach

Testing issues are becoming more and more important with the quick development of both digital and analog circuit industry. In this paper, we study the utilization of evolutionary algorithms for optimal input vectors derivation of neural network based analog and mixed signal circuits fault diagnosis approach and compare the results with normal method. We have introduced a new procedure which uses the n-detection test set concept and selects the input samples in a way that for each case of fault injection, there will be at least n sample to activate that fault. This procedure performs the optimization in two ways. The first one called speed method generates samples in a way that acceptable decision strength and lower training phase duration would be achieved. The second one called stamina method generates samples in a way that best decision strength and higher training phase duration would be achieved. Experimental results demonstrate that the obtained input voltages yields fault diagnosis with increased fault coverage and high decision strength.