一种降低基带芯片功耗的时钟策略及改进方案

为了更为有效地降低手机基带芯片中GSM通讯模块的功耗,将门控时钟策略和GSM通讯模块的特点结合起来,用硬件电路精确控制GSM通讯模块的休眠,并且对可能遇到提前唤醒的场景提出了改进方法,EDA软件仿真和FPGA验证了该方法可以达到明显的功耗优化效果.     

时钟芯片SD2203AP的应用设计

SD2203AP是一种内置晶振、SRAM、两线式IIC总线通信方式的高精度免调校时钟芯片,该时钟模块具有集成度高,与MCU的通信接口电路简单,内部时钟精度高且功耗低的特点,文中详细介绍谊模块的工作原理、应用举例(单片机STC89C54控制SD2203AP的硬件接口电路设计和软件编程方法)及应用中的一些注意事项。     

S1240时钟和信号音模块

(一)时钟和信号音模块的组成和作用:图1是时钟和信号音模块的组成方框图。由图可见,该模块的终端主要由时钟的产生和分配、数字信号音的产生和分配以及测试信号分析器等部分组成。时钟的产生和分配部分包括外时钟接口电路、中央时钟电路和时钟分配电路,其作用是产生主时钟8.192MHz信号,分配至各机架各模块。数字信号音的产生和分配部分包括数字信号音发生电路、时间信号电路和信号音分配电路。实际上,时钟分配电路和信号音分配电路是合在一起的,其作用是产生各种数字信号音,如拨号音、忙音等,还能示出时、分、秒和1/10秒等数字时间信号,分配至各机架各模块。测试信号分析器(图1中     

一种存储器低失配时钟输出电路

随着动态随机存取存储器(DRAM)的工作频率不断提高,导致DRAM芯片的时钟输出电路中的时钟树信号线路径需要完全匹配,甚至相同.本文论述了一种低失配时钟输出电路设计,包括时钟产生电路、供电模块、以及多个时钟输出模块,时钟产生电路与时钟输出模块之间均通过时钟树信号线连接,供电模块与时钟输出模块之间均通过电源线连接,时钟树...     

PowerPC8270数据处理模块的PCI接口设计

针对嵌入式计算机系统中的PCI通信应用,文章提出了一种PowerPC8270数据处理模块的PCI接口设计。文章先介绍了该模块的系统结构,然后主要介绍了PowerPC8270处理器的PCI总线接口硬件结构、时钟生成和驱动软件设计思想,可满足多种应用需求。     

PLL IC构成简单的数字移相器

在某些信号处理和时钟分配应用场合,移相器是一种主要模块。另一个重要应用是在作为数字相位检测器的基准方面。图1中的电路,尤其适用于评估相位检测器,该电路只使用了二块符合工业标准的IC (CD4046和LM311),它依赖于数字PLL(锁相环路)技术。     

基于AS8228的单相电子式电能表设计

介绍了奥地利微电子公司推出的能量计量集成电路AS8228的主要特点,以及其内部单/双路电流输入能量测量前端、液晶显示驱动器、4线串行外设接口、实时时钟、系统控制模块等的结构和功能,并给出了AS8228在单相电子式电能表设计中的典型应用电路.     

高速时钟驱动电路的优化设计

随着系统电路工作频率的不断提高,在应用中对系统互连和电路间的时钟传输提出了更高的要求。提出了一款基于LVDS(低压差分信号)接口的时钟分路驱动电路,该电路可输出四路时钟信号,工作频率在2 GHz以下,电路采用了0.13μm CMOS工艺,电源电压为3.3 V,内部集成了LDO电路。主要阐述了如何通过内部预加重电路,共模电压稳定电路,占空比调整电路等模块来优化电路的性能,并配合仿真进行了相关的分析。     

PTC—2型免编程电脑化日历实时钟模块的应用

本文介绍的ＲＴＣ模块主要是针对公共场所日历实时钟（大屏幕）ＬＥＤ显示而设计，可带安全日参数的新产品。它的显示接口特色和ＳＰＩ通讯串口使其应用更为广泛。能方便地应用于多屏同步时钟，世界时钟，正计时／倒计时安全日时钟及工业测控领域。     

基于单片机的时钟电路设计

设计一种简易的时钟电路,电路由单片机最小系统、电平转换模块、按键输入模块,时钟模块、液晶显示模块组成.电路以STC89C52单片机为控制核心,控制串行实时时钟芯片M41ST85W进行时钟读、写、报警操作.     

VxWorks下基于辅助时钟的通用定时器设计

VxWorks操作系统以其强实时性、可剪裁性等特点得到了广泛应用,但其并未提供通用的定时器模块。为解决某机载发射装置控制盒中VxWorks系统的精确定时问题,文中在分析多种定时方式的基础上,利用辅助时钟中断,通过创建定时节点,构造节点链表,设计了基于辅助时钟的通用定时器模块。经测试表明,该模块实现了毫秒级定时,满足了某发射装置的定时需求,并为今后类似系统的精确定时需求提供了方便。     

基于改进FFT算法的OFDM调制/解调模块设计

文章对传统FFT算法进行了改进,改进后的算法将N点DFT分解成二维√N点DFT的组合,在结构上更适合于用流水线方式实现FFT.文章首先对算法进行了推导,然后基于该算法设计了一个64点、32位字长的定点IFFT/FFT模块,用于802.11a中OFDM的调制/解调.与传统的流水线FFT比较,该模块中的复数乘法运算全部采用移位相加操作完成,因而消除了乘法器及旋转因子ROM的使用,降低了功耗.最后,对该模块进行了验证仿真.结果表明,在流水线饱和的情况下,该模块完成一个64点的FFT运算只需要8个时钟周期,在20MHZ时钟频率下,该模块的功耗为0.26W,完全能满足移动通信中对于高速度、低功耗的要求.     

Realization of a discrete Fourier transform (DFT) module for incorporation in FFT processors

For applications requiring high-speed and in-place treatment, it is often advantageous to realize special-purpose computers. This paper describes a discrete Fourier transform (DFT) module for incorpration in fast Fourier transform (FFT) processors. The module is highly suitable for real input applications requiring high-speed transformations. It attributes one point to all frequency channels in one clock cycle. This treatment is not only well suited for the present technology, but appears to be more attractive in view of recent trends in digital circuitry.     

Over GHz low-power RF clock distribution for a multiprocessordigital system

Conventional interconnections for digital clock distribution pose a severe power consumption problem for GHz clock distribution due to transmission line losses. Therefore, we have proposed an RF clock distribution (RCD) scheme for high-speed digital applications, in particular a multiprocessor system using global clocking. This paper first reports system power and signal integrity analysis results including skew, jitter, impedance mismatch, and noise for RF clock distribution,especially in the GHz range. Based on this analysis, a novel signal integrity design methodology for RF clock distribution systems is proposed. The clock skew created by process parameter variations are modeled and predicted. The system comprises a RF clock transmitter as a clock generator, an H-tree with junction couplers as a clock distributing network and a RF receiver as a digital clock-recovery module. Flip-chip interconnections for the chip-to-substrate assembly and 0.35 μm TSMC CMOS technology for the RF clock receiver are assumed. EMI analysis for 2 GHz 16-node-board-level RF clock distribution networks is conducted using 3D full-wave EM simulation. Finally, the RCD as a low power and high performance clocking method is demonstrated using HP's Advanced Design System (ADS) simulation, considering microwave frequency interconnection models and process parameter variations. In addition, test vehicles for both 2 GHz 16-node and 5 GHz 64-node board-level RF clock distribution networks were implemented and measured using thin, low-loss, and low permittivity Rogers^Lt; RO3003 high-frequency organic substrate     

基于Verilog的模拟前端时序的实现方法

针对如何高精度、高速实现模拟前端时序的问题,提出了一种用于平板探测器的模拟前端时序的Verilog实现方法。Verilog语言的编程整体上采用模块化设计,主要包含电荷采集模块、数据读出模块和计数器模块。利用锁相环技术设置各模块不同的时钟信号,通过编写有限状态机和改进型计数器实现各模块的时序。仿真结果表明,该编程方法满足了时序高精度实现的需求,具有运行速度快、灵活性高等特点,达到了预期效果。     

基于PCI-e和PCI-x总线的XMC/PMC载板设计

为了灵活地实现VPX系统中功能的扩展,设计了一种采用PCI-e总线和PCI-x总线的XMC/PMC功能载板。该载板通过P1-P6连接器与不同功能板卡连接,由HD68接口实现外界与载板之间数据通信,并介绍了以PCI-e开关模块和PCI-e转PCI-x模块为主的系统方案。对其中的转换模块、开关模块、存储模块、电源模块和时钟模块进行了详细介绍。在电路设计过程中,通过仿真保证高速电路的信号完整性。最后通过与AD板卡进行调试,验证了XMC/PMC设计可行性。     

Programmable 2D linear filter for video applications

A fully integrated 2-D linear filter including a line buffer for a 7×7 kernel is presented. To run the filter in real time at video clock frequencies, an array of pipelined carry-save adders was used as a very fast arithmetic unit. The filter chip contains 292451 transistors on a silicon area of 135 mm². The maximum clock frequency under worst-case conditions for technology and temperature was simulated to be 20 MHz. The main blocks are designed as independent parameterizable modules. The line buffer and the arithmetic unit are available as macros in a standard cell library for semicustom design. With these macros a semicustom chip for image enhancement in a X-ray system was produced. This chip works with a system frequency of 13 MHz. The line buffer module is used in another full-custom image processing chip-a two-dimensional rank order filter with a kernel size of also 7×7. This chip contains more than 300000 transistors on a silicon area of 103 mm². In this case the module containing the 1-D FIR (finite impulse response) filters is replaced by additional pixel delays and a sorter module. Simulations have shown that the chip could work with clock frequencies up to 20 MHz     

集成式石英谐振加速度计倍频电路设计

谐振式加速度计可以将加速度转换为频率信号,在导航、姿态控制等加速度计的应用领域,采集信号需要限定在较短时间内,为了满足应用的要求,基于一种单基片集成式石英谐振器,通过现场可编程门阵列(FPGA)实现了一种针对集成式石英谐振加速度计的倍频电路设计方案,包括时钟自适应模块和锁相环。时钟自适应模块根据当前输入信号产生锁相环基准时钟并将输入信号进行倍频。离心机加速度测试结果表明,当测量时间由1 s缩短为0.125 s时,传感器标度因数为3 173 Hz/g(g=9.8 m/s²),线性相关系数R²=0.999 32,与未倍频时相比,标度因数与线性度基本保持不变,所设计的倍频电路可应用于石英谐振加速度计的信号处理及数据采集系统中。     

A 10-gb/s CMOS clock and data recovery circuit with an analog phase interpolator

This paper presents a 10-Gb/s clock and data recovery (CDR) circuit for use in multichannel applications. The module aligns the phase of a plesiochronous system clock to the incoming data by use of phase interpolation. Thus, coupling between voltage-controlled oscillators (VCOs) in adjacent channels can be avoided. The controller for the phase interpolator is realized with analog circuitry to overcome the speed and phase resolution limitations of digital implementations. Fabricated in a 0.11-/spl mu/m CMOS technology the module has a size of 0.25/spl times/1.4 mm/sup 2/. The power consumption is 220 mW from a supply voltage of 1.5 V. The CDR exceeds the SDH/SONET jitter tolerance specifications with a pseudo random bit sequence of length 2/sup 23/-1 and a bit-error rate threshold of 10/sup -12/. The re-timed and demultiplexed data has an rms jitter of 3.2 ps at a data rate of 2.7 Gb/s.