|
|||||
|
|
| 一种降低基带芯片功耗的时钟策略及改进方案 | |
| 引用本文： | 程曾,李同合,马林,何有志,郑晓庆.一种降低基带芯片功耗的时钟策略及改进方案[J].微电子学与计算机,2012,29(2):91-94. |
| 作者姓名： | 程曾 李同合 马林 何有志 郑晓庆 |
| 作者单位： | 1. 西安交通大学电子与信息工程学院微电子学系,陕西西安,710049 2. 西安电子科技大学微电子学院,陕西西安,710071 3. 西安交通大学电子物理与器件教育部重点实验室电子与信息工程学院,陕西西安,710049 |
| 摘 要： | 为了更为有效地降低手机基带芯片中GSM通讯模块的功耗,将门控时钟策略和GSM通讯模块的特点结合起来,用硬件电路精确控制GSM通讯模块的休眠,并且对可能遇到提前唤醒的场景提出了改进方法,EDA软件仿真和FPGA验证了该方法可以达到明显的功耗优化效果. |
| 关 键 词： | 低功耗 时钟策略 GSM休眠定时器 基带芯片 高精度 |
Clock Strategy and Its Enhancement for Reducing Baseband Chip＇s Power Dissipation |
|
| CHENG Zeng,LI Tong-he,MA Lin,HE You-zhi,ZHENG Xiao-qing.Clock Strategy and Its Enhancement for Reducing Baseband Chip＇s Power Dissipation[J].Microelectronics & Computer,2012,29(2):91-94. | |
| Authors: | CHENG Zeng LI Tong-he MA Lin HE You-zhi ZHENG Xiao-qing |
| Affiliation: | 1 Dept.of Microelectronics,School of Electronic and Information Engineering,Xi′an Jiaotong University, Xi′an 710049,China;2 School of Microelectronics,Xidian University,Xi′an 710071,China; 3 Key Laboratory of Physical Electronics and Devices of the Ministry of Education,School of Electronic and Information Engineering,Xi′an Jiaotong University,Xi′an 710049,China) |
| Abstract: | In order to reduce the power dissipation of GSM module of baseband chips more effectively,this paper combined clock gating and GSM module’s feature together,and controlled its power consumption precisely with hardware circuits;and enhancement method was proposed also for pre-wakeup situations.The results of EDA simulation and FPGA verification show that the proposed method can reduce the power dissipation obviously. |
| Keywords: | low power clock strategy GSM sleep timer baseband chip high precise |
| 本文献已被 CNKI 万方数据 等数据库收录！ | |
