热的LDI: 满足HDI印刷术的挑战

关于PCB制造商能力的高密度互连技术的定位领域问题。为了达到目前和未来封装技术所需的互连密度的要求,印制电路板工业将持续地移向更小的图形尺寸。当图形尺寸减小和信号传输速度增加时,对于低缺陷密度和高质量的制造工艺之要求将强烈地增加了。这样一来,HDI电路的制造,也就是导线和连接盘的图形生产在制造加工过程中将变成一个重要的舞台。     

半导体芯片中等离子损伤的解决方案

在研发一套基于0.18μm工艺的全新半导体芯片时,由于芯片工艺的要求我们将标准0.18μm工艺流程中的接触孔蚀刻阻挡层由原来的UVSIN+SION改为SIN,但却引进了PID(等离子体损伤)的问题。当芯片的关键尺寸减小到0.18μm时,栅氧化层变得更薄,对等离子体的损伤也变得更加敏感。所以如何改善PID也成为这款芯片能否成功量产的重要攻坚对象。这一失效来源于接触孔阻挡层的改变,于是将改善PID的重点放在接触孔蚀刻阻挡层之后即后段工艺上。后段的通孔蚀刻及钝化层的高密度等离子体淀积会产生较严重的等离子体损伤,因此如何改善这两步工艺以减少等离子体损伤便成为重中之重。文中通过实验验证了关闭通孔过蚀刻中的磁场以及减小钝化层的高密度等离子体淀积中的溅射刻蚀功率可以有效改善芯片的等离子体损伤。通过这两处的工艺优化,使得PID处于可控范围内,保证了量产的芯片质量。     

刚挠结合板非导通孔到图形对位能力研究

因软硬结合板有三维组装特性,部分产品根据其特殊的应用场景,要求控制顶层和底层零件的对准度,针对此类要求,客户零件贴装需以非导通孔为基准对位贴合,避免零件偏移,需控制软硬结合板基准点即非导通孔到顶层和底层图形的对位公差为±0.10 mm,软硬结合板受软性材料涨缩变形的影响,按常规的制作工艺,图形到非导通孔的对位能力CpK<1.0,该能力无法实现批量生产;本文主要研究提升高密度互连类软硬结合板中非导通孔到图形的对位公差能力,通过分析孔到图形对位的影响因素,简化图形对位的层次,重新排列非导通孔的加工过程,实现顶层和底层的图形到非导通孔的间距同时满足±0.10 mm的公差要求,提升图形到非导通孔的间距能力CpK>1.67,满足批量生产的要求,同时,为行业内提升软硬结合板非导通孔到图形的对位能力提供参考。     

纳米工艺提高了LSI铜布线的可靠性

位于日本东京的NEC公司开发出了一种能够在不牺牲布线性能的情况下提高下一代LSI电路中铜布线的可靠性的纳米工艺。该工艺包括两个部分:即在通孔连接界面上插入一层超薄的钛(Ti)薄膜,以及采用氟化碳氮化物(FCN)薄膜来解决长期困扰半导体制造商的一个难题,就是在0.1μm以下的多层布线中出现的可靠性下降。当把钛薄膜加到位于铜布线之间的芯片顶层和底层时,它起胶合剂的作用,可将由应力造成的位移,以及通常与密封装置中的通孔破裂相关联的电迁移减小93%。该工艺通过减小应力和抑制铜迁移的方法在铜通孔处实现了更强的键合。Ti的表面电阻…     

化学外延方式的嵌段共聚物定向自组装

定向自组装(DSA)是一种新型的光刻分辨率增强技术,为了探究制约DSA应用于大规模集成电路制造的因素,采用仿真手段评估了DSA工艺条件以及不同版图设计对DSA的影响。基于Cahn-Hilliard方程,模拟了不同"吸附"强度及退火时间下的线条图形光刻轮廓,分析了上述工艺条件对光刻结果的影响,发现增加退火时间、增强衬底的"吸附"强度可以有效减小电路制造缺陷。基于7 nm设计规则,改变引导图形周期,得到线条图形线宽粗糙度(LWR)以及通孔图形的光刻轮廓图,分析了引导图形周期和LWR及轮廓图质量的关系,得出当引导图形周期为2倍共聚物自然周期(2L0)时,可以得到更好的光刻图形质量,并通过2L0周期扰动实验进一步验证了该结论。     

员工培训实用基础教程（二十五）

本小节重在探讨积层印制电路板制造工艺,其中主要包括制造芯板、导通孔形成、导通孔孔壁形成导电层和最后形成导体图形等内容。     

铜互连应力模拟分析

建立了三维有限元模型,采用ABAQUS有限元分析软件,模拟计算了Cu互连系统中的热应力分布;通过改变通孔直径、铜线余量、层间介质等,对比分析了互连结构对热应力分布的影响。结果表明,互连应力在金属线中通孔正下方铜线顶端处存在极小值,应力和应力梯度在下层铜线互连顶端通孔两侧处存在极大值。应力和应力梯度随着通孔直径或层间介质材料介电常数的减小而下降,应力随铜线余量长度的减小而增大。双通孔结构相对于单通孔结构而言,靠近下层金属线末端的通孔附近应力较大,但应力梯度较小。     

双面印制电路的印刷、吸附、催化加成法制备工艺

开发出了一种双面印制电路板的加成法制备工艺,其具体流程包括：（1）在基板上需要双面导通的部位钻孔,并浸涂离子吸附功能油墨;（2）在基板双面印刷掩膜,暴露出线路图形与通孔部位;（3）基板浸入硝酸银溶液中,吸附银离子至图形和通孔表面;（4）除去掩膜,使用化学镀铜的方法使表面线路和通孔金属化,得到所需双面印制电路板。本工艺可以将双面印制电路线路和通孔一步加成制造,简化了工序,降低了成本,节约了材料。     

Cu互连应力迁移失效有限元分析

为研究铜互连系统中各因素对残余应力及应力迁移失效的影响,建立了三维有限元模型,用ANSYs软件分析计算了Cu互连系统中的残余应力分布情况,并对比分析了不同结构、位置及层间介质材料的互连系统中的残余应力及应力梯度.残余应力在金属线中通孔正下方M2互连顶端最小,在通孔内部达到极大值,应力梯度在Cu M2互连顶端通孔拐角底部位置达到极大值.双通孔结构相对单通孔结构应力分布更为均匀,应力梯度更小.结果表明,空洞最易形成位置由应力和应力梯度的大小共同决定,应力极大值随通孔直径和层间介质介电常数的减小而下降,随线宽和重叠区面积的减小而上升.应力梯度随通孔直径、层间介质介电常数和重叠区面积的减小而下降,随线宽减小而上升.     

消除硅通孔侧壁刻蚀损伤的方法

硅通孔刻蚀是TSV技术的重要工序步骤,采用标准博世（Bosch）工艺刻蚀硅通孔（宽为150μm）,发现硅通孔侧壁出现多处刻蚀损伤。通过优化Bosch工艺参数增加沉积保护,消除了硅通孔侧壁刻蚀损伤问题,通孔开口差值,即通孔下开口宽度与通孔上开口宽度的差,从原来的22μm减小到13μm。利用优化后的工艺配方对硅通孔和硅腔(宽为1 500μm)同时进行刻蚀时,发现硅腔刻蚀后会产生硅针,不能应用到实际生产。经过多轮次Bosch工艺参数调整,把Bosch工艺沉积步骤的偏置功率设置为10 W,同时解决了硅通孔侧壁刻蚀损伤和硅腔刻蚀出现硅针问题,最终成功应用到MEMS环形器系列产品当中。     

LTPS TFT层间绝缘层过孔刻蚀的工艺优化

为了适应LTPS TFT LCD显示屏超高分辨率极细布线的趋势,降低LTPS TFT层间绝缘层过孔刻蚀带来的良率损失,提高产品品质,本文研究了LTPS TFT层间绝缘层过孔刻蚀的工艺优化。实验以干法刻蚀为主刻蚀,湿法刻蚀为辅刻蚀的方式,既结合干法刻蚀对侧壁剖面角及刻蚀线宽的精确控制能力,又利用了湿法刻蚀高刻蚀选择比的优良特性,改善了层间绝缘层刻蚀形貌,减少干法刻蚀对器件有源层的损伤,避免有源层被氧化,防止刻蚀副产物污染开孔表面。实验结果表明,干法辅助湿法刻蚀能基本解决刻蚀过程中过刻、残留的问题,使得层间绝缘层过孔不良良率损失减少73%以上,且TFT源漏电极接触电阻减小约90%,器件开态电流提升约15%。干法辅助湿法刻蚀是一种优化刻蚀工艺,提升产品性能的新方法。     

Atomic Layer Deposition Assisted Pattern Multiplication of Block Copolymer Lithography for 5 nm Scale Nanopatterning

5‐nm‐scale line and hole patterning is demonstrated by synergistic integration of block copolymer (BCP) lithography with atomic layer deposition (ALD). While directed self‐assembly of BCPs generates highly ordered line array or hexagonal dot array with the pattern periodicity of 28 nm and the minimum feature size of 14 nm, pattern density multiplication employing ALD successfully reduces the pattern periodicity down to 14 nm and minimum feature size down to 5 nm. Self‐limiting ALD process enable the low temperature, conformal deposition of 5 nm thick spacer layer directly at the surface of organic BCP patterns. This ALD assisted pattern multiplication addresses the intrinsic thermodynamic limitations of low χ BCPs for sub‐10‐nm scale downscaling. Moreover, this approach offers a general strategy for scalable ultrafine nanopatterning without burden for multiple overlay control and high cost lithographic tools.     

Using the photolysis of chemically modified gel films preparing ITO fine patterned thin films

A novel technique for the fabrication of tin-doped indium oxide (ITO) fine patterning in sol-gel technology is presented in this paper. The fabricated ITO fine patterning could be obtained through a process which combines film fabrication with film etching. ITO films have good comprehensive property of visible transmittance and electrical conductivity, consequently they have been extensively used as coating electrodes. Indium nitrate (In(NO/sub 3/)/sub 3/.4.5H/sub 2/O) and stannic chloride ( SnCl/sub 4/.5H/sub 2/O) were used as starting materials which were modified with benzytone (BzAcH). The chelate complexes containing indium ions were produced during the process which of forming photosensitive ITO/BzAcH gel films through sol-gel technique. It was found that the gel films are sensitive to both the ultraviolet (UV) light irradiation and their solubility on solvents as well. For example, ethanol was reduced remarkably while the UV absorption peak disappeared with the dissociation of the chelate complexes correspondingly by means of UV-vis and IR spectrophotometers. Utilizing these characteristics, a fine pattern was obtained by irradiation of UV light on the ITO/BzAcH gel films through a pattern mask. of the fine patterned ITO films were heat treated at 500/spl deg/C for 15 min, the optical, electrical properties and the surface element components were examined by X-ray photoelectron spectroscopy (XPS) spectra in this work.     

Electroless‐Plated Gold Contacts for High‐Performance,Low Contact Resistance Organic Thin Film Transistors

Deposition of metallic electrodes on a semiconductor medium is an indispensable factor in governing carrier injection, and a metal/semiconductor contact that can be formed via solution process is highly desired in printed electronics. However, fine‐patterning the solution processes of metallic electrodes without damaging the excellent electronic properties of organic semiconductors (OSCs) is still a challenge. In this work, electroless plating, a metal coating technique that involves auto‐catalytic reaction in an aqueous solution, is used to fabricate top‐contact organic thin‐film transistors (OTFTs). An electroless‐plated gold pattern with a spatial resolution of 10 micrometers is transferred and laminated on a monolayer of OSCs to serve as a hole‐injection electrode. The fabricated OTFTs exhibit reasonably high field‐effect mobility of up to 13 cm² V^?1 s^?1 and decent contact resistance as low as 120 Ω · cm, which implies that an ideal metal/semiconductor contact can be realized. This electroless plating technique can provide possibilities for practical mass production of organic integrated circuits because it is in principle cost‐effective, capable of covering large areas, high‐vacuum free, and environmentally friendly.     

Excimer Laser Projection Photoablation Patterning of Metal Thin Films for Fabrication of Microelectronic Devices and Displays

A nonlithographic process is demonstrated for patterning Al, Cr, Cu, Ni, Ti, and W thin films, which are widely used in microelectronic and display fabrication. A projection photoablation process using 248-nm-deep ultraviolet radiation from a KrF excimer laser was used to pattern a polyimide film coated on a SiN layer deposited on glass. The photoablation-patterned polyimide film was used as a sacrificial layer in a lift-off patterning process for the metal films, which resulted in clean metal patterns with fine line-edge definition being fabricated after lift-off. This process provides a simpler and more economical patterning technique compared to conventional lithography methods, eliminating the developing and etching steps.     

钝化层沉积工艺对过孔尺寸减小的研究

为了适应TFT-LCD小型化与窄边框化以及在面板布线精细化的趋势,提高工艺设计富裕量以及增加面板的实际利用率,研究了通过改变钝化层(PVX)的沉积工艺来减小液晶面板阵列工艺中连接像素电极与漏极的过孔(VIA)尺寸的方案,通过设计实验考察了影响过孔大小的钝化层的主要影响因素(黑点、倒角、顶层钝化层沉积厚度,顶层钝化层沉积压力),得出了在不改变原有刻蚀方式基础之上使过孔的尺寸降低20%～30%的优化方案,并对其进行了电学性能评价(Ion:开态电流、Ioff:关态电流、Vth:阈值电压、Mobility:迁移率),从而获得了较佳的减小过孔尺寸的方案,提高了产品品质。     

Resist pattern peeling assessment in DUV chemically amplified resist

As device size shrinks resist line peeling becomes more challenging. In this paper we studied the resist pattern peeling based on resist processing parameters and type of bottom antireflective coating (BARC), for patterning trench structures with different duty ratios, in copper and low k dual damascene process. To minimize resist poisoning in dual damascene process, acetal-based resist was used. Significant improvement in via poisoning was observed with this chemistry as compared to environmentally stable chemically amplified resist chemistry but at the cost of pattern peeling. In order to solve pattern peeling problem we tried to analyze key factors such as compatibility with BARC, post-exposure bake, BARC curing, adhesion and their effects. Pitch dependency on pattern peeling margin is observed.     

Novel method for simultaneous formation of wires and vias of a printed circuit board using nanoporous body

A new type of a flexible printed circuit board with landless vias is developed using a novel method called interconnection via nanoporous structure (INPS). This method can make wires and vias of the printed circuit board simultaneously by a single photo-exposure process. A new photo-induced selective plating method was used to impregnate a nanoporous substrate with copper, and a new photomask was designed, which constitutes of a completely vacant large hole for via and aggregation patterns of very fine holes for wire. Because of the simple process, the INPS board is characterized by landless vias and very fine circuit. Owing to the structure, it is also characterized by flexibility and detachable wires.     

TFT-LCD过孔接触电阻研究

研究了过孔接触电阻变化规律,并进行机理分析,为优化薄膜晶体管的过孔设计提供依据。首先,运用开尔文四线检测法对不同大小、形状、数量的钼/铝/钼结构的栅极和源/漏层金属与氧化铟锡连接过孔的接触电阻进行测试。然后,通过扫描电子显微镜、能量色散X射线光谱仪和聚焦离子束显微镜对过孔内部形貌进行表征。最后,对过孔接触电阻变化规律进行机理分析。实验结果表明:过孔面积越大,接触电阻越小;过孔面积相同时,长方形过孔的接触电阻小于正方形过孔的接触电阻,多小孔的接触电阻小于单大孔的接触电阻,栅极金属与氧化铟锡的过孔接触电阻小于源/漏层金属与氧化铟锡的过孔接触电阻。为了降低钼/铝/钼与氧化铟锡连接过孔的接触电阻,过孔面积尽可能最大化,采用长方形过孔优于正方形过孔,多小过孔优于单大孔设计,同时优化过孔刻蚀工艺,减少过孔内顶层钼的损失。     

Patterning of organic layers using negative and positive working Top-CARL process

The Top-CARL process is a technique for patterning organic materials some tens of microns thick by top-resist silylation and pattern transfer via oxygen reactive ion etching. The influence of exposure dose, temperature and top-resist layer thickness on the silylation process is studied. A dyed version of the resist is examined. Its polarity can be changed from negative to positive working by addition of a small amount of a photo base.