Nanoscale strained-Si MOSFET physics and modeling approaches: a review

An attempt has been made to give a detailed review of strained silicon technology. Various device models have been studied that consider the effect of strain on the devices, and comparisons have been drawn. A review of some modeling issues in strained silicon technology has also been outlined. The review indicates that this technology is very much required in nanoscale MOSFETs due to its several potential benefits, and there is a strong need for an analytical model which describes the complete physics of the strain technology.     

Fabrication of ultra-thin strained silicon on insulator

A bond and etch back technique for the fabrication of 13-nm-thick, strained silicon directly on insulator has been developed. The use of a double etch stop allows the transfer of a thin strained silicon layer with across-wafer thickness uniformity comparable to the as-grown epitaxial layers. Surface roughness of less than 1 nm was achieved. Raman analysis confirms strain remains in the thin silicon layers after the removal of the SiGe that induced the strain. Ultra-thin strained silicon-on-insulator (SSOI) substrates are promising for the fabrication of ultra-thin body and double-gate, strained Si metal-oxide semiconductor field-effect transistors (MOSFETs).     

Fundamentals of silicon material properties for successful exploitation of strain engineering in modern CMOS manufacturing

Semiconductor industry has increasingly resorted to strain as a means of realizing the required node-to-node transistor performance improvements. Straining silicon fundamentally changes the mechanical, electrical (band structure and mobility), and chemical (diffusion and activation) properties. As silicon is strained and subjected to high-temperature thermal processing, it undergoes mechanical deformations that create defects, which may significantly limit yield. Engineers have to manipulate these properties of silicon to balance the performance gains against defect generation. This paper will elucidate the current understanding and ongoing published efforts on all these critical properties in bulk strained silicon. The manifestation of these properties in CMOS transistor performance and designs that successfully harness strain is reviewed in the last section. Current manufacturable strained-silicon technologies are reviewed with particular emphasis on scalability. A detailed case study on recessed silicon germanium transistors illustrates the application of the fundamentals to optimal transistor design.     

45nm工艺及材料的最新动态

介绍了45nm芯片、工艺和设备的最新动态。英特尔、TI、IBM、特许、英飞凌和三星都推出了45nm功能芯片。45nm主要工艺包括光刻、应变硅、低k电介质、Cu互连、高k电介质和离子注入等。光刻工艺采用193nmArF/浸没式光刻机。45nm工艺中应变硅技术已步入第三代,它综合采用双应力衬垫、应力记忆和嵌入SiGe层。     

应用400℃低温Si技术制备应变Si沟道pMOSFET

在利用分子束外延方法制备SiGe pMOSFET中引入了低温Si技术.通过在Si缓冲层和SiGe层之间加入低温Si层,提高了SiGe层的弛豫度.当Ge主分为20%时,利用低温Si技术生长的弛豫Si1-xGex层的厚度由UHVCVD制备所需的数微米降至400nm以内,AFM测试表明其表面均方粗糙度(RMS)小于1.02nm.器件测试表明,与相同制备过程的体硅pMOSFET相比,空穴迁移率最大提高了25%.     

不同直径张应变锗材料对光谱和晶体质量的影响

绝缘体上张应变锗材料是通过能带工程提高锗材料光电性能得到的一种新型半导体材料,在微电子和光电子领域具有重要的应用前景.采用微电子技术中的图形加工方法以及利用锗浓缩的技术原理,在绝缘体上硅(SOI)材料上制备了绝缘体上张应变锗材料.喇曼与室温光致发光(PL)测试结果表明,不同圆形半径的绝缘体上锗材料张应变均为0.54％.对于绝缘体上张应变锗材料,应变使其发光红移的效果强于量子阱使其发生蓝移的效果,总体将使绝缘体上张应变锗材料的直接带发光峰位红移.同时0.54％张应变锗材料的直接带发光强度随着圆形半径的增大而减弱,这主要是因为圆形半径大的样品其晶体质量较差.该材料可进一步用于制备锗微电子和光电子器件.     

Strain analysis of arsenic-doped silicon using CBED rocking curves of low-order reflections

Local lattice strains of semiconductor devices have been so far examined using higher order Laue zone (HOLZ) line patterns of convergent-beam electron diffraction (CBED). Recently, strain analyses in highly strained regions near interfaces have been reported using split HOLZ line patterns. In the present paper, it is demonstrated for arsenic-doped silicon that the use of CBED rocking curves of low-order reflections provides a promising new tool for the determination of strain distributions of highly strained specimen areas. That is, the anomalous intensity increase in the CBED rocking curves of low-order reflections is explained using a model structure with a strain gradient in the electron beam direction, which is similar to the models used for the split HOLZ line patterns.     

Experimental study of Auger recombination, gain, and temperaturesensitivity of 1.5 μm compressively strained semiconductorlasers

The effect of strain on Auger recombination has been studied using the differential carrier lifetime technique in both lattice matched InGaAs-InP and compressively strained quaternary quantum wells. It is found that Auger recombination is reduced in strained devices. The transparency carrier density and differential gain of both lattice matched and strained devices have been obtained by gain and relative intensity noise measurement. A reduction of the transparency carrier density is observed in the strained device. However, no differential gain increase is seen. The temperature sensitivity of the threshold current density of both lattice matched and strained devices has been fully studied. Physical parameters contributing to the temperature sensitivity of the threshold current density have been separately measured, and it is shown that the change in differential gain with temperature is a dominant factor in determining the temperature sensitivity of both lattice matched and strained devices     

基于悬浮张应变锗纳米薄膜的电致发光增强

基于准直接带隙的材料特性,锗材料已经成为硅基光电集成的研究热点。本文利用高应力氮化硅薄膜将应力引入锗纳米薄膜中,并成功制备出张应变锗纳米薄膜发光二极管。实验结果显示,制备出的发光二极管在室温下的电致发光有红移现象,这是由于应力作用下的锗材料能带变化引起的。另外,当在锗纳米薄膜中引入的应变达到1.92%时,所制备的发光二极管在1876nm峰值波长处的发光强度显著增加,证明了张应变锗纳米薄膜的直接带隙复合发光,进一步证实了应变锗材料在硅基光电集成应用上的广阔前景。     

Low-Temperature Epitaxy of Compressively Strained Silicon Directly on Silicon Substrates

We report epitaxial growth of compressively strained silicon directly on (100) silicon substrates by plasma-enhanced chemical vapor deposition. The silicon epitaxy was performed in a silane and hydrogen gas mixture at temperatures as low as 150°C. We investigate the effect of hydrogen dilution during the silicon epitaxy on the strain level by high-resolution x-ray diffraction. Additionally, triple-axis x-ray reciprocal-space mapping of the samples indicates that (i) the epitaxial layers are fully strained and (ii) the strain is graded. Secondary-ion mass spectrometry depth profiling reveals the correlation between the strain gradient and the hydrogen concentration profile within the epitaxial layers. Furthermore, heavily phosphorus-doped layers with an electrically active doping concentration of ~2 × 10²⁰ cm⁻³ were obtained at such low growth temperatures.     

张应变锗薄膜制备技术的研究进展

由于与硅集成电路工艺兼容的张应变锗薄膜在光电器件如光电探测器、调制器,特别是发光器件中具有潜在的应用前景,使其得到了广泛关注.然而,在锗薄膜中引入可控的、大的张应变是个挑战.综述了张应变锗薄膜制备技术的研究进展,重点介绍了在锗薄膜中引入张应变的外延技术、应变转移技术、应变浓缩技术和机械应变技术的工艺流程和实验结果,并讨论了它们的优点和缺点.采用应变浓缩技术制备的厚度为350 nm的锗薄膜微桥的单轴张应变和微盘的双轴张应变分别达到了4.9％和1.9％,可将锗调制为直接带隙材料,适用于锗激光器的研制.     

应变Si/(001)Si_(1-x)Ge_x价带结构

应变SiCMOS技术是当前国内外研究发展的重点,在高速/高性能器件和电路中有极大的应用前景。基于(001)面弛豫Si1-xGex衬底上生长的张应变Si的价带E(k)-k关系模型,研究获得了[100]和[001]晶向的价带结构及相应的空穴有效质量。结果表明,与弛豫材料相比,应变引起了应变Si/(001)Si1-xGex价带顶的劈裂,且同一晶向族内沿[001]和[100]两个晶向的价带结构在应力的作用下不再对称,相应的空穴有效质量随Ge组份有规律地变化。价带空穴有效质量与迁移率密切相关,该结论为Si基应变PMOS器件性能增强的研究及导电沟道的应力与晶向设计提供了重要理论依据。     

High-mobility FET in strained silicon

Suitably strained silicon exhibits a mobility anisotropy that can be used to advantage in field-effect transistors. The desired strain can be achieved through heteroepitaxy.     

Dislocation configurations in Si/SixGe1-x strained layer heterostructures

The details of dislocation node structures in (100) Si/Si_xGe_1-x heterostructures are shown through weak-beam transmission electron microscopy studies. It is shown that the resulting configurations are due to dislocation glide on {100} and {111} planes, as well as the interaction between dissociated dislocations. It is shown that similar observations have been made in bulk deformed silicon. The implications of the observations on the issue of strain relaxation in strained layer heterostructures is also discussed.     

SiGe PMOSFET性能模拟

由于受热力学基本定律的限制 ,Si集成电路技术的发展已经日益接近极限 ,而 Si Ge材料的引入使得占据小于 1GHz频段的 Si产品可以进一步覆盖 2～ 30 GHz的 RF和无线通信市场。根据前人的材料研究工作 ,在普通 Si器件性能模拟的基础上 ,进一步研究长沟应变 Si Ge器件的模拟 ,引入了插值所得的近似因子以修正 silvaco中隐含的 Si Ge能带模型和迁移率参数。然后依据修正后的模型对 Si Ge PMOS进行更为精确的二维模拟     

A 90-nm logic technology featuring strained-silicon

A leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low-/spl kappa/ CDO for high-performance dense logic is presented. Strained silicon is used to increase saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10% and 25%, respectively. Using selective epitaxial Si/sub 1-x/Ge/sub x/ in the source and drain regions, longitudinal uniaxial compressive stress is introduced into the p-type MOSEFT to increase hole mobility by >50%. A tensile silicon nitride-capping layer is used to introduce tensile strain into the n-type MOSFET and enhance electron mobility by 20%. Unlike all past strained-Si work, the hole mobility enhancement in this paper is present at large vertical electric fields in nanoscale transistors making this strain technique useful for advanced logic technologies. Furthermore, using piezoresistance coefficients it is shown that significantly less strain (/spl sim/5 /spl times/) is needed for a given PMOS mobility enhancement when applied via longitudinal uniaxial compression versus in-plane biaxial tension using the conventional Si/sub 1-x/Ge/sub x/ substrate approach.     

Strains and crystal lattice defects arising in macroporous silicon under oxidation

The deformation behavior of a macroporous silicon wafer subjected to high-temperature oxidation has been studied, and the basic parameters describing the sample bending and subsequent stress relaxation when oxide is removed are determined. X-ray diffractometry and topography were used to determine the sample bending radius and lattice parameters, and to reveal the areas of dislocation generation. The strain of a silicon lattice in oxidized macroporous Si is about 10^?4, and it decreases by an order of magnitude after oxide dissolution. The plastic part of the strain is accompanied by the generation of dislocations in the most strained regions of a structure, i.e., at the interfaces between the porous layer and substrate in the vertical direction and between the central porous region and the pore-free edge in the horizontal plane. The dislocation density is ～10⁴ cm^?2.     

Modeling of enhancement factor of hole mobility for strained silicon under low stress intensity

In order to quantitatively characterize the enhancement of hole mobility of strained silicon under different stress intensity conditions, changes of hole effective mass should be studied. In the paper, strained silicon under in-plane biaxially tensile strain based on (0 0 1) substrate and longitudinal uniaxially compressive strain along 〈1 1 0〉 are investigated thoroughly. By solving the Hamiltonian of valence band using K·P model, we can obtain the relationship of density of state effective mass (m_DOS), conductivity effective mass (m_C) and splitting energy in valence band energy with stress intensity for both biaxially tensile strain and uniaxially compressive strain. For the stress intensity less than 1 GPa, the paper presents the models of enhancement factor of hole mobility under the biaxially tensile strain and uniaxially compressive strain. The results show that biaxially tensile strain of silicon cannot enhance hole mobility under low stress intensity, while uniaxially compressive stress of silicon can enhance hole mobility greatly.     

硅光栅的制作与应用

硅是一种良好的近红外材料。硅光栅的发展迄今已有20多年历史,在制作方法和应用上都有了较大的发展。硅光栅的微加工工艺可以分为体硅工艺和面硅工艺,这些微加工方法在技术上与微电子及微机械工艺可以兼容。本文介绍了硅光栅的制作及其在不同领域的应用。     

Review: Semiconductor Piezoresistance for Microsystems

Piezoresistive sensors are among the earliest micromachined silicon devices. The need for smaller, less expensive, higher performance sensors helped drive early micromachining technology, a precursor to microsystems or microelectromechanical systems (MEMS). The effect of stress on doped silicon and germanium has been known since the work of Smith at Bell Laboratories in 1954. Since then, researchers have extensively reported on microscale, piezoresistive strain gauges, pressure sensors, accelerometers, and cantilever force/displacement sensors, including many commercially successful devices. In this paper, we review the history of piezoresistance, its physics and related fabrication techniques. We also discuss electrical noise in piezoresistors, device examples and design considerations, and alternative materials. This paper provides a comprehensive overview of integrated piezoresistor technology with an introduction to the physics of piezoresistivity, process and material selection and design guidance useful to researchers and device engineers.