A Novel On-Chip Amplifier for Fast I DD Current Monitoring

A novel circuit of the low-voltage application-specific amplifier is proposed and analyzed. A wide-band current amplifying cell is developed as a central part of the amplifier structure. The amplifier is designed for a built-in-current-sensor, on-chip circuitry used in high-frequency power supply current monitoring and test applications. It could be implemented with analog, digital, or mixed-signal cores in an integrated system-on-chip environment. The current amplifier has been fabricated in 0.13 and 0.18 μm CMOS technology processes with 1.2 and 1.8 V power supply, respectively. The impacts of technology scaling on amplifier's performances have been investigated as well. With sensitivity better than 500 nA, the 0.13 μm design achieves the gain-bandwidth product of 6.8 GHz, low frequency current gain of 48 dB, high linearity for the input current range of (?15 μA, 15 μA), and power consumption of 5.2 mW.     

All-digital A/D converter TAD with high-resolution and low-power for sensor/RF digitization

For achieving both high resolution and low power of a sensor/RF interface, time-domain processing using full-digital circuits, which deals with only two voltage levels (i.e., V _in-supply-voltage and ground-level), is presented. In a much broader sense, digital circuits can be used for time-domain processing instead of conventional analog signal processing. In this study, an all-digital 6- to 16-bit adaptive sensor-interface ADC is experimentally evaluated for high-resolution and low-power operation along with high scalability. The circuit architecture is completely digital, using a ring-delay-line (RDL) driven by an input voltage V _in as its power supply. Resolutions can be controlled by setting its conversion time T _cv, resulting in 16 bit (1 kS/s, 34 μW) and 6 bit (1 MS/s, 48 μW) with a prototype IC in a low-cost 0.65-μm (650-nm) digital CMOS, achieving the sensor digitizer (sensor-digitization product) of a pressure sensor ASIC. The all-digital structure has been scaled into a 0.18-μm technology, and the test IC presented a higher performance with 28 μV/LSB (160-kS/s). Finally, as an RF digitization application, the circuit is demonstrated to realize the time-domain processing of an RF signal, working as both mixer and ADC, achieving minimum/maximum detectable sensitivity of 0.7-μVrms/100-mVrms, respectively, for a 40-kHz sine wave at the LNA input terminal of a 0.18-μm digital CMOS one-chip radio-controlled clock receiver IC.     

A Design of a Low-Voltage Current-Mode Fully-Differential Analog CMOS Integrator Using FG-MOSFETs and Its Implementation

In the field of analog signal processing, there is a strong need for low-voltage and low-power integrated circuits. Especially in the mobile communication circuitry, an analog signal processing circuit must be fed by dry batteries of 1–1.5 V. This paper presents a design and implementation of a current-mode fully-differential analog CMOS integrator operable with such a low supply voltage. This integrator is built with a cross-coupled matched pair of 3-input FG(Floating Gate)-MOSFETs, a matched pair of 2-input FG-MOSFETs, and four bias current sources. In this circuit, both a low apparent threshold voltage of FG-MOSFETs and voltage signal summation at the floating gates are effectively utilized to enable the circuit operation with a low supply voltage and to simplify the circuit configuration. The influence of the common-mode signal and noise to the signal processing are minimized by adopting fully-differential structure. The performance of the proposed integrator circuit is predicted by theoretical analysis and by HSPICE simulations. The circuit works as an integrator in the frequency range 4–750 MHz at a 1.5 V supply voltage and dissipates DC power of about 70 W. The proposed circuit was fabricated by a Motorola 1.2 m double-poly CMOS process in the chip fabrication program of VLSI Design and Education Center (VDEC).     

Design and verification of a high performance analog switch circuit

A double-pole double-throw analog switch circuit structure with low power consumption, low on-resistance and capable of transmitting negative signals is designed in this paper, which has been developed in 0.18 μm BCD technology. The analog switch circuit is providing about 5 V high swing signal transmission for 2.7–5 V supply voltage in the temperature range of ??40 to 85 °C. The shortcomings of traditional analog switch structure are large on-resistance, large power consumption, etc. In this paper, the charge pump structure of the gate voltage bootstrap switch is designed to overcome the backgate effect, to control the turn-on and turn-off of each switching MOS transistor. A dynamic comparator structure is used to enhance the signal transmission capability, so that the analog switch can transmit negative signal. The measurement results show that under the voltage of 2.7–5 V, the overall designed circuit consumes 92 μW. The on-resistance of the analog switch is 3.9 Ω, and the leakage current is 12 nA. The analog switch has a good signal transmission and shutdown capabilities while occupying an area of 0.67 mm².

     

Structural Test Approach for Embedded Analog Circuits Based on a Built-in Current Sensor

This paper presents a test method based on the analysis of the dynamic power supply current, both quiescent and transient, of the circuit under test. In an off-chip measurement, the global interconnect impedance associated with the chip package and the test equipment and, also, the chip input/output cells will complicate the extraction of the information provided by the current waveform of the circuit under test. Thus, the supply current is measured on-chip by a built-in current sensor integrated in the die itself. To avoid the effective reduction of the voltage supply, the measurement is performed in parallel by replicating the current that flows through selected branches of the analog circuit. With the aim of reducing the test equipment requirements, the built-in current sensor output generates digital level pulses whose width is related to the amplitude and duration of the circuit current transients. In this way the defective circuit is exposed by comparing the digital signature of the circuit under test with the expected one for the fault-free circuit. A fault evaluation has been carried out to check the efficiency of the proposed test method. It uses a fault model that considers catastrophic and parametric faults at transistor level. Two benchmark circuits have been fabricated to experimentally verify the defect detection by the built-in current sensor. One is an operational amplifier; the other is a structure of switched current cells that belongs to an analog-to-digital converter.     

Design and implementation of a hybrid circuit system for micro sensor signal processing

This paper covers a micro sensor analog signal processing circuit system(MASPS) chip with low power and a digital signal processing circuit board implementation including hardware connection and software design. Attention has been paid to incorporate the MASPS chip into the digital circuit board.The ultimate aim is to form a hybrid circuit used for mixed-signal processing,which can be applied to a micro sensor flow monitoring system.     

应用于微传感器信号处理的混合电路系统的设计与实现

研究旨在设计一个应用于飞行器机翼表面边界层的流动监测系统。该系统主要由微传感器及其信号处理电路构成。本文的主要工作是微传感器信号处理电路系统中低功耗的模拟电路芯片的及相关数字电路板的设计,重点在于完成模拟电路芯片的具体应用。目的是将该模拟电路芯片良好地应用于该数字电路板,使其协同工作,构成一个完整的混合电路系统,以便在较低的成本下,较好地完成微传感器信号处理的任务。     

Ultra low power phase detector and phase-locked loop designs and their application as a receiver

In this paper, we present a new low power down-conversion mixer design with single RF and LO input topology which consumes 48 μW power. Detailed analysis of the mixer has been provided. Using the presented mixer as a phase-detector, a low power phase-locked loop (PLL) has been designed and fabricated. A PLL based receiver architecture has been developed and analyzed. The circuit has been fabricated through 0.13 μm CMOS technology. Dissipating 0.26 mW from a 1.2 V supply, the fabricated PLL can track signals between 1.62 and 2.49 GHz. For receiver applications, the energy per bit of the receiver is only 0.26 nJ making it attractive for low power applications including wireless sensor networks.     

An A/D interface based on ∑Δ modulator for thermal vacuum sensor ASICs

A new ∑Δ modulator architecture for thermal vacuum sensor ASICs is proposed.The micro-hotplate thermal vacuum sensor fabricated by surface-micromachining technology can detect the gas pressure from 1 to 105 Pa.The amplified differential output voltage signal of the sensor feeds to the ∑Δ modulator to be converted into digital domain.The presented ∑Δ modulator makes use of a feed-forward path to suppress the harmonic distortions and attain high linearity.Compared with other feed-forward architectures presented before,the circuit complexity,chip area and power dissipation of the proposed architecture are significantly decreased.The correlated double sampling technique is introduced in the 1st integrator to reduce the flicker noise.The measurement results demonstrate that the modulator achieves an SNDR of 79.7 dB and a DR of 80 dB over a bandwidth of 7.8 kHz at a sampling rate of 4 MHz.The circuit has been fabricated in a 0.5μm 2P3M standard CMOS technology.It occupies an area of 5 mm2 and dissipates9 mW from a single 3 V power supply.The performance of the modulator meets the requirements of the considered application.     

A single-chip CMOS APS camera with direct frame difference output

A complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) camera chip with direct frame difference output is reported in this paper. The proposed APS cell circuit has in-pixel storage for previous frame image data so that the current frame image and the previous frame image can be read out simultaneously in differential mode. The signal swing of the pixel circuit is maximized for low supply voltage operation. The pixel circuit occupies 32.2×32.2 μm² of chip area with a fill factor of 33%. A 128×98 element prototype camera chip with an on-chip 8-bit analog-to-digital converter has been fabricated in a 0.5-μm double-poly double-metal CMOS process and successfully tested. The camera chip consumes 56 mW at 30 frames/s with 3.3 V power supply     

A 1.5-V current-mode CMOS sample-and-hold IC with 57-dB S/N at 20MS/s and 54-dB S/N at 30 MS/s

A new video-speed current-mode CMOS sample-and-hold IC has been developed. It operates with a supply voltage as low as 1.5 V, a signal-to-noise ratio (S/N) of 57 dB and 54 dB with a 1-MHz input signal at clock frequencies of 20 and 30 MHz, and a power dissipation of 2.3 mW. It consists of current-mirror circuits with the node voltages at the input and the output terminals which are kept constant in all phases of the input signal by the use of low-voltage operational amplifiers; this reduces the signal current dependency. The low-voltage operational amplifier consists of a MOS transistor and a constant current source in a common-gate amplifier configuration. Only two analog switches in differential form were used to construct the differential sample-and-hold circuit. This minimizes the error caused by the switch feed through, and thus high accuracy can be realized. Since there is no analog switch in the input path, it is possible to convert the input signal voltage to a current by simply connecting an external resistor. The circuit was fabricated using standard 0.6-μm MOS devices with normal threshold voltages (V_th) of +0.7 V (nMOS) and -0.7 V (pMOS)     

加速度传感器信号处理集成电路的研制

设计并制作了一种用于差分电容式加速度传感器的信号处理电路。该电路具有模拟和脉宽调制两种输出方式 ,能够将差分电容的变化通过模拟电平和输出脉冲信号的占空比表征 ,实现了对差分电容式加速度传感器信号的测量。电路中集成了自检测驱动单元。电路采用 4 μmP阱CMOS工艺制作。初步测试结果表明 :在 1～ 5 pF内 ,电路的灵敏度为 10 .7V/ pF ,可满足大多数差分电容式传感器信号处理的要求。     

Design of a CMOS low-power and low-voltage four-quadrant analog multiplier

A New CMOS four-quadrant analog multiplier is presented in this paper. The proposed multiplier is suitable for low supply-voltage operation and its power consumption is also very low. The proposed circuit has been simulated with the HSPICE and simulation results are given to confirm the feasibility of the proposed analog multiplier. According to the simulation results, under the supply voltage of 1.5 V, the input range of the proposed multiplier can be 120 mV and the corresponding maximum linearity error is less than 3.2%. Moreover, the power dissipation of the proposed circuit is only 6.7 μW. The proposed circuit is expected to be useful in analog signal processing applications.     

无源UHF RFID电子标签模拟前端设计

提出了一种符合ISO/IEC 18000-6B标准的高性能无源UHF RFID电子标签模拟前端,在915MHz ISM频带下工作时其电流小于8μA.该模拟前端除天线外无外接元器件,通过肖特基二极管整流器从射频电磁场接收能量.该RFID模拟前端包括本地振荡器、时钟产生电路、复位电路、匹配网络和反向散射电路、整流器、稳压器以及AM解调器等.该芯片采用支持肖特基二极管和EEPROM的Chartered 0.35μm 2P4M CMOS工艺进行流片,读取距离大于3m,芯片面积为300μm×720μm.     

Low-voltage, high-speed CMOS analog latched voltage comparator using the “flipped voltage follower” as input stage

The design and characterization of a low-voltage, high-speed CMOS analog latched voltage comparator based on the flipped voltage follower (FVF) cell and input signal regeneration is presented. The proposed circuit consists of a differential input stage with a common-mode signal detector, followed by a regenerative latch and a Set-Reset (S-R) latch. It is suitable for successive-approximation type’s analog-to-digital converters (ADC), but can also be adapted for use in flash-type ADCs. The circuit was fabricated using 0.18 μm CMOS technology, and its measured performance shows 12-bit resolution at 20 MHz comparison rate and 1 V single supply voltage, with a total power consumption of 63.5 μW.     

A four-channel CMOS codec filter circuit “SICOFI-4”

Cost reduction by integration of complex mixed analog-digital systems on a single chip and an excellent yield to area ratio is a major goal for IC design in the nineties. In this paper, a four-channel codec-filter chip for analog subscriber lines in ISDN-orientated networks is presented, giving an exceptional example for high level system implementation combined with parallel DSP integration and analog circuitry with high performance. The chip combines four analog frontends, digital signal processing realized by different approaches for a sophisticated filter concept in addition with test strategies including digital and analog BIST. The circuit is fabricated in a standard 1-μm CMOS technology, needs a single 5-V power supply, and can easily be programmed to world-wide different country specifications and applications     

CMOS integrated MPP tracker with analog power measurement at the PV converter input

An integrated converter controller with maximum power point (MPP) regulation in 0.35 μm CMOS for photovoltaic (PV) applications is reported. The implemented MPP tracker bases on a perturb and observe algorithm and acquires the information concerning the power flow via an analog processing circuit which is connected at the switched mode converter input respectively the output of the attached PV string of nine cells. There the solar cell current is measured via a very low-ohmic shunt resistor of 1 mΩ and analogously multiplied with the cell voltage. As output the fabricated test chip directly generates a 530 kHz PWM signal for the external switched mode converter. Measurements show that under similar conditions analog MPP tracking of the converter input power improves the robustness with respect to settling times of the power path compared to those topologies at which the power is measured at the converter output. Between 0.4 and 7.5 A photocurrent the chip achieves tracking efficiencies better than 99.5 % while the power consumption is only 750 μW and a very low chip area demand of 0.043 mm² for the MPP tracking core is achieved.     

An ultra-low power energy-efficient microsystem for hydrogen gas sensing applications

This paper presents a fully integrated power management and sensing microsystem that harvests solar energy from a micro-power photovoltaic module for autonomous operation of a miniaturized hydrogen sensor. In order to measure H₂ concentration, conductance change of a miniaturized palladium nanowire sensor is measured and converted to a 13-bit digital value using a fully integrated sensor interface circuit. As these nanowires have temperature cross-sensitivity, temperature is also measured using an integrated temperature sensor for further calibration of the gas sensor. Measurement results are transmitted to the base station, using an external wireless data transceiver. A fully integrated solar energy harvester stores the harvested energy in a rechargeable NiMH microbattery. As the harvested solar energy varies considerably in different lighting conditions, the power consumption and performance of the sensor is reconfigured according to the harvested solar energy, to guarantee autonomous operation of the sensor. For this purpose, the proposed energy-efficient power management circuit dynamically reconfigures the operating frequency of digital circuits and the bias currents of analog circuits. The fully integrated power management and sensor interface circuits have been implemented in a 0.18 μm CMOS process with a core area of 0.25 mm². This circuit operates with a low supply voltage in the 0.9–1.5 V range. When operating at its highest performance, the power management circuit features a low power consumption of less than 300 nW and the whole sensor consumes 14.1 μA.     

An energy-efficient spike encoding circuit for speech edge detection

In speech processing applications, the instantaneous bandwidth of speech can be used to adaptively control the performance of an audio sensor’s analog front end. Extracting the instantaneous bandwidth of speech depends on the detection of speech edges in the time–frequency plane. In this paper, we propose a spike encoding circuit for real-time and low-power speech edge detection. The circuit can directly encode the signal’s envelope information—an important feature to identify the speech edge—by temporal spike density without additional envelope extraction. Furthermore, the spike encoding circuit automatically adapts its resolution to the amplitude of the input signal, which improves the encoding resolution for small signal without increasing the power consumption. We use the nonlinear dynamical approach to design this circuit and analyze its stability. We also develop a linearized model for this circuit to provide the design intuition and to explain its adaptive resolution. Fabricated in 0.5-μm CMOS process, the spike encoding circuit consumes 0.3-μW power and the experimental results are presented.     

Design techniques of low-power embedded EEPROM for passive RFID tag

This paper presents an optimized embedded EEPROM design approach which has reduced the power significantly in a short-range passive RFID tag. The proposed array control circuit employs an improved structure to minimize the leakage of memory bit cells. With the proposed array circuit design, the passive RFID tag can operate drawing a low quiescent current. The RFID tag with the proposed EEPROM was fabricated in a standard 0.35-μm four-metal two-poly CMOS process. Measurement results show that the erasing/writing current is 45 μA, and reading current consumption is 3 μA with a supply voltage of 3.3 V. The data read time is 300 ns/bit.