A 0.003-mm2, 0.35-V, 82-pJ/conversion ultra-low power CMOS all digital temperature sensor for on-die thermal management

In this paper, a 0.35 V, 82 pJ/conversion ring oscillator based ultra-low power CMOS all digital temperature sensor is presented for on-die thermal management. We utilize subthreshold circuit operation to reduce power and adopt an all-digital architecture, consisting of only standard digital gates. Additionally, a linearization technique is proposed to correct the nonlinear characteristics of subthreshold MOSFETs. A bulk-driven 1-bit gated digitally controlled oscillator is designed for the temperature sensing node. Also, a 1-bit time-to-digital converter is employed in order to double the fine effective resolution of the sensor. The proposed digital temperature sensor has been designed in a 90-nm regular V _T CMOS process. After a two-point calibration, the sensor has a maximum error of ?0.68 to +0.61 °C over the operating temperature range from 0 to 100 °C, while the effective resolution reaches 0.069 °C/LSB. Under a supply voltage of 0.35 V, the power dissipation is only 820 nW with the conversion rate of 10K samples/s at room temperature. Also, the sensor occupies a small area of 0.003 mm².     

An 87 fJ/conversion-step 12 b 10 MS/s SAR ADC using a minimum number of unit capacitors

This work proposes a 12 b 10 MS/s 0.11 μm CMOS successive-approximation register ADC based on a C-R hybrid DAC for low-power sensor applications. The proposed C-R DAC employs a 2-step split-capacitor array of upper seven bits and lower five bits to optimize power consumption and chip area at the target speed and resolution. A V_CM-based switching method for the most significant bit and reference voltage segments from an insensitive R-string for the last two least significant bits minimize the number of unit capacitors required in the C-R hybrid DAC. The comparator accuracy is improved by an open-loop offset cancellation technique in the first-stage pre-amp. The prototype ADC in a 0.11 μm CMOS process demonstrates the measured differential nonlinearity and integral nonlinearity within 1.18 LSB and 1.42 LSB, respectively. The ADC shows a maximum signal-to-noise-and-distortion ratio of 63.9 dB and a maximum spurious-free dynamic range of 77.6 dB at 10 MS/s. The ADC with an active die area of 0.34 mm² consumes 1.1 mW at 1.0 V and 10 MS/s, corresponding to a figure-of-merit of 87 fJ/conversion-step.     

A 12-bit self-calibrating SAR ADC achieving a Nyquist 90.4-dB SFDR

This paper describes a 10 or 12 bit programmable successive approximation register ADC for bridge stress monitoring systems requiring high-resolution, high linearity, low power and small size. Its sampling rate is scalable, from 0 to 200 kS/s. The proposed ADC employs a novel time-domain comparator with offset cancellation. Prototyped in a 0.18-μm, 6MIP CMOS process, the ADC, at 12 bit, 100 kS/s, achieves a Nyquist SNDR of 68.74 dB (11.13), an SFDR of 90.36 dB, while dissipating 579.6 μW from a 1.8-V supply. The on-chip calibration improves the DNL from +0.2/?0.74 LSB to +0.23/?0.25 LSB and INL from +1.27/?0.97 LSB to +0.41/?0.4 LSB.     

L, C and X band integrated synthetic aperture radar (SAR) receiver

An integrated receiver consisting of RF front ends, analog baseband (BB) chain with an analog to digital converter (ADC) for a synthetic aperture radar (SAR) implemented in 130 nm CMOS technology is presented in this paper. The circuits are integrated on a single chip with a size of 10.88 mm². The RF front end consists of three parallel signal channel intended for L, C and X-band of the SAR receiver. The BB is selectable between 50 and 160 MHz bandwidths through switches. The ADC has selectable modes of 5, 6, 7 and 8 bits via control switches. The receiver has a nominal gain of 40 and 37 dB and noise figure of 11 and 13.5 dB for 160 MHz BB filter at room temperature for L-band and C-band, respectively. The circuits, which use a 1.2 V supply voltage, dissipate maximum power of 650 mW with 50 MHz BB and 8 bit mode ADC, and maximum power of 800 mW with 160 MHz BB and 8 bit mode ADC.     

Algorithmic ADC operating with a single reference voltage for PLL-based chemical sensing applications

This paper deals with the design of an algorithmic switched-capacitor analog-to-digital converter (ADC), operating with a single reference voltage, a single-ended amplifier, a single-ended comparator, and presenting a small input capacitance. The ADC requires two clock phases per conversion bit and N clock cycles to resolve the N-bits. The ADC achieves a measured peak signal-to-noise-ratio (SNR) of 49.9 dB and a peak signal-to-noise-and-distortion-ratio (SNDR) of 46.7 dB at P_in = ?6dBFS with a sampling rate of 0.25 MS/s. The measured differential-non-linearity and integral-non-linearity are within +0.6/?0.5 and +0.2/?0.5 LSB, respectively. The ADC power consumption is 300 μW and it is implemented in 90 nm CMOS technology with a single power supply of 1.2 V. The ADC saves power at system-level by requiring only a single reference voltage. At system level, this solution is therefore not only robust but competitive as well.     

A 12 b 8 kS/s 16 μW 0.35 μm CMOS algorithmic ADC for sensor interface in ubiquitous environments

This work proposes a 12 b 8 kS/s ultra-low-power CMOS algorithmic analog-to-digital converter (ADC) for sensor interface applications such as accelerometers and gyro sensors requiring high-resolution, low-power, and small size simultaneously. The proposed ADC employs switched-bias power reduction and bias sharing circuits to minimize chip area and power dissipation. A signal-insensitive all directionally symmetric layout technique based on a double-poly CMOS process reduces capacitor mismatch in the multiplying D/A converter for 12 b-level high accuracy without additional conventional calibration schemes. Two independently generated currents with the same negative temperature coefficient are subtracted from each other to implement temperature- and supply-insensitive current and voltage references on-chip. The prototype ADC in a 0.35 μm 2P4M CMOS technology demonstrates a measured differential non-linearity and integral non-linearity within 0.15 and 0.56 LSB at 12 b and shows a maximum signal-to-noise-and-distortion ratio and spurious-free dynamic range of 68 and 77 dB at 8 kS/s, respectively. The ADC with an active die area of 0.70 mm² consumes 16 μW at 8 kS/s and 2.5 V.     

A 132 Mb/s, 1bit 4224 M samples/s sub-sampling, low-complexity and energy-efficient BPSK transceiver for all-digital 3–5 GHz IR-UWB

In this paper, a 3–5 GHz impulse radio ultra wideband BPSK transceiver is presented. A new all-digital architecture is applied in the proposed transceiver. The transceiver has no mixer and low complexity. The transmitter employs a RLC network response filter to achieve the adjustable pulse parameters, which includes pulse width, pulse bandwidth and pulse amplitude. Considering the low duty ratio, a proposed on/off output buffer in the transmitter is applied to save the power consumption. To simplify the receiver, the radio frequency input signal is amplified and sampled directly by a 1bit 4224 MHz sub-sampling ADC. The ADC comprises by 16 paralleled comparators for low power. Each comparator operates at 264 MHz and can be self-calibrated. The transceiver is implemented in SMIC 0.13 μm CMOS process at the supply of 1.2 V. The measured results show the adjustable parameters: the pulse amplitude is from 110 to 370 mV, the pulse width is from 900 to 1,600 ns and the pulse bandwidth is from 2.0 to 2.78 GHz. The data rate is 132 Mb/s between the transceiver. The transmitter and the receiver only consume 18.2 and 330 pJ/pulse, respectively. The receiver sensitivity is ?75 dBm at the bit error rate of 10^?3.     

A 0.6 V and 0.395 pJ/bit nonius TDC for a passive RFID pressure sensor tag

This work presents a nonius time to digital converter (TDC) adapted to a passive RF identification (RFID) pressure sensor tag. The proposed converter exploits the characteristics of time-based sensor interfaces and allows reducing voltage supply and power consumption while maintaining resolution and conversion efficiency. The nonius TDC has been designed and fabricated using the TSMC 90 nm standard CMOS technology. The main blocks of the converter are described and both the resolution adjustment and measurement processes are explained in detail. Measurement results show 10.49 bits of effective resolution for an input time range from 28.19 to 42.93 μs. With a sampling rate of 19 KS/s the converter has a conversion efficiency of 0.395 pJ/bit with a voltage supply of only 0.6 V. This characteristics in the proposed nonius TDC enables an increased reading range of the passive RFID pressure sensor tag.     

基于EPC Class0协议超高频温度传感器无源电子标签

提出了实现具有温度传感功能的RFID无源标签芯片电路的设计思路,结合900MHz超高频EPC Class0协议,提出电子标签结构及参考电路,包括射频前端接收电路、数字逻辑控制部分、温度传感及量化和存储器四部分组成。采用Chartered0.35μm CMOS工艺流片、测试。温度量化采用一个低功耗8位逐次逼近模数转化器实现,输出温度量化误差在0～90℃范围内为±2℃。芯片测试工作电流20.7μA(不包含存储器)。     

Experimental implementation of a 14 bit 80 kSPS non-binary cyclic ADC

This paper presents a prototype of 14 bit 80 kSPS non-binary cyclic ADC without high accuracy analog components and complicated digital calibration. Since the redundancy of non-binary ADC tolerates the non-idealities of analog components such as capacitor mismatch and finite amplifier DC gain, the design consideration of this high accuracy ADC can be only focused on the capacitance of sampling capacitor to satisfy the overall kT/C noise target, the drivability and linearity of amplifier without any high accuracy analog components. The proposed proof-of-concept cyclic ADC has been designed and fabricated in TSMC 90 nm CMOS technology. Measured SNDR = 81.9 dB is achieved at Fs = 80 kSPS with a simple radix-value estimation technique. No other complicated digital calibration is used to compensate the non-linearity of ADC caused by MOM capacitors and a poor gain of the amplifier as low as 66 dB. Measured DNL is ? 0.6/+ 0.67 LSB and INL is ? 1.2/+ 1.6 LSB. Prototype ADC dissipates 8mW at supply voltage is 3.3 V in analog circuits.     

An 8/10 bit 200/100MS/s configurable asynchronous SAR ADC

This paper presents an asynchronous 8/10 bit configurable successive approximation register analog-to-digital converter (ADC). The proposed ADC has two resolution modes and can work at a maximal sampling rate of 200 and 100MS/s for 8 bit mode and 10 bit mode respectively. The ADC uses a custom-designed 1 fF unit capacitor to reduce the power consumption and settling time of capacitive DAC, a dynamic comparator with tail current to minimize kickback noise and improve linearity. Moreover, asynchronous control technique is utilized to implement the ADC in a flexible and energy-efficient way. The proposed ADC is designed in 90 nm CMOS technology. At 100MS/s and 1.0 V supply, the ADC consumes 1.06 mW and offers an ENOB of 9.56 bit for 10 bit mode. When the ADC operates at 8 bit mode, the sampling rate is 200MS/s with 1.56 mW power consumption from 1.0 supply. The resulted ENOB is 7.84 bit. The FOMs for 10 bit mode at 100MS/s and 8 bit mode at 200MS/s are 14 and 34 fJ/conversion-step respectively.     

Delta–Sigma A/D Conversion Via Time-Mode Signal Processing

In this paper, a signal processing methodology is proposed that performs delta-sigma (DeltaSigma) analog-to-digital (A/D) conversion on voltage signals while implementing all the circuits in a digital CMOS logic style. This methodology, called time-mode (TM) signal processing, uses time-difference variables as an intermediate signal between the input voltage and the digital output. The resulting low-cost silicon devices offer very compact, low-power, high-speed, and robust A/D converter (ADC) alternatives. A first-order DeltaSigma ADC is implemented using this methodology. Two ICs were fabricated in a 0.18- mum CMOS technology to demonstrate the feasibility of the TM DeltaSigma ADC approach. The first IC implements a single-ended input design while a differential design was fabricated in the second IC. Experimental results reveal that these devices can achieve 7-9-bit resolutions within 125-400-kHz bandwidths, while occupying areas smaller than 50 mum ×50 mum and consuming less than 800 muW.     

A 53mW IQ pipelined ADC for WLAN front end

This paper presents an analog to digital converter (ADC) architecture suitable for wideband wireless receiver system. The in-phase (I) and quadrature (Q) ADCs work independently, but share on-chip reference buffer and non-overlapped clock generation block for balance between two channels. The single ADC core consists of one front sample and hold amplifier, four cascade of 2.5 bit pipeline stages with pseudo-class AB opamp shared between adjacent stages and one 2 bit backend flash stage. The prototype was fabricated in standard 130 nm CMOS process and occupied silicon area of 0.62 mm². Performance of 66 dB spurious-free-dynamic-range is measured at 80 MS/s with 1 Vpp input signal. The power dissipation of the whole chip is only 53 mW from a 1.1 V supply.     

A high-speed CMOS image sensor with a 11-bit column-parallel A/D converter

This article presents a high-speed, high-linearity 400 × 320 pixel CMOS image sensor with column parallel ADC. The pixel readout circuit is integrated in the 320 columns at one side of the pixel array and all columns consume 16 mW power provided from the 2.5 V power supply. A technique for accelerating conversion speed using two step single slope structure is developed. This new method has more advantages than conventional ramp ADC from viewpoint of speed and resolution. A prototype 11-bit ADC is implemented in 0.25 μm CMOS technology. Moreover, an overall SNR of 63.8 dB can be achieved at 0.5 Msample/s. The power dissipation of all 320 column-parallel ADCs with the peripheral circuits consumes 76 mW.     

用于CMOS图像传感器的9位10MS/s低功耗流水线ADC

提出了一个用于CMOS图像传感器的9位10MS/s、低功耗流水线ADC.为降低功耗,该设计通过采用低功耗、宽摆幅的带有增益增强结构的放大器以及将所有单元共用偏置电路的技术来实现.共用偏置技术需要仔细的版图设计和在电路中加入大的去耦合电容来实现.此外,设计中也采用电容阵列DAC来降低功耗.同时,为了增大信号处理范围,设计中还采用低阈值电压的MOS管.该ADC采用4M-1P的0.18μm CMOS工艺设计制造.对芯片的测试结果表明该设计的功耗仅为7mW,相对其他设计是相当低的.该ADC已经应用于30万像素图像传感器系统中,该系统已经流片、测试.     

A 0.6 V 100 KS/s 8–10 b resolution configurable SAR ADC in 0.18 μm CMOS

A resolution configurable ultra-low power SAR ADC in 0.18 μm CMOS process is presented. The proposed ADC has maximum sampling rate of 100 KS/s with configurable resolution from 8 to 10 b and operates at a supply of 0.6 V. Two-stage bootstrapped switch and voltage boosting techniques are introduced to improve the performance of the ADC at low voltage. To reduce the power consumption of the analog components of the ADC, monotonic capacitor switching procedure and fully dynamic comparator are utilized. The implementation of dynamic logic further reduces the power of the digital circuits. Post-layout simulation results show that the proposed SAR ADC consumes 521 nW and achieves an SNDR of 60.54 dB at 10 b mode, resulting in an ultra-low figure-of-merit of 6.0 fJ/conversion-step. The ADC core occupies an active area of only 350 × 280 μm².     

A 10-bit 50-MS/s redundant SAR ADC with split capacitive-array DAC

A new architecture for successive-approximation register analog-to-digital converters (SAR ADC) using generalized non-binary search algorithm is proposed to reduce the complexity and power consumption of the digital circuitry. The proposed architecture is based on the split capacitive-array DAC with a simple switching logic as compared to the conventional non-binary SAR ADC architecture. A 10-bit 50-MS/s SAR ADC is designed based on the proposed architecture in a 0.18 μm CMOS technology. Simulation results show that at a supply voltage of 1.2 V, the SAR ADC achieves a peak signal-to-noise-and-distortion ratio of 59.5 dB, and a power consumption of 1.3 mW, resulting in a figure of merit of 33 fJ/conversion-step.     

A 1.0-V 6-b 40 MS/s time-domain flash ADC in 0.18 μm CMOS

This paper presents a 6-bit low power low supply voltage time-domain comparator. The conventional voltage comparison is moved to time-domain so as to remove pre-amplifier and latch, which enables its feasibility to low supply voltage. The voltage-to-time converter is realized by the proposed linear pulse-width-modulation. The set-up time of the D flip-flop determines the sampling rate of the converter. The resistive averaging relaxes the matching requirement of the parallel comparison cells. The total input capacitance is decreased to less than 40fF in this architecture. The above digital-intensive setting makes the analog-to-digital converter (ADC) benefit from technology scaling in both power consumption and sampling rate. The prototype ADC is fabricated in SMIC 0.18 μm CMOS process. At 40 MS/s and 1.0-V supply, it consumes 540 μW and achieves an effective-number-of-bit of 5.43, resulting in a figure-of-merit of 0.31 pJ/conversion-step and active area of 0.1 mm².     

A multisampling time-domain CMOS imager with synchronous readout circuit

A novel multisampling time-domain architecture for CMOS imagers with synchronous readout and wide dynamic range is proposed. The proposed multisampling architecture requires only a single bit per pixel memory instead of 8 bits which is typical for time-domain active pixel architectures. The goal is to obtain a time-domain imager with high dynamic range that requires lower number of transistors per pixel in order to achieve higher fill-factor. The maximum frame rate is analyzed as a function of number of bits and array size. The analysis shows that it is possible to achieve high frame rates and operate in video mode having 10 bit pixel data resolution. Also, we present analysis of the impact of comparator offset voltage on the fixed pattern noise. The architecture was implemented in an imager prototype with 32 × 32 pixel array fabricated in AMS CMOS 0.35 μm and was characterized for sensitivity, noise and color response. The pixel size is 30 μm × 26 μm and it is composed of an n+/psub photodiode, a comparator and a D flip-flop with a 16% fill-factor.     

A 12-bit 10-MS/s SAR ADC with a weighted sampling time technique applied to C-DAC

This paper presents a low power 12-bit 10-MS/s successive approximation register (SAR) analog-to-digital convert (ADC) for bio-signal signal processing in wearable sensor systems. A weighted sampling time technique applied to a capacitor digital to analog converter (C-DAC) is employed to reduce the power consumption of the conventional SAR ADC with minimum performance sacrifice. The proposed technique helped reduce its energy consumed by MSB, MSB-1, MSB-6, and MSB-7 capacitors by more than 40% compared with that of the conventional C-DAC. Another technique, a voltage scaling method is also employed to lower the power supply voltage from 1.2 to 0.6 V for all the digital logics except the output registers, such that it results in a power reduction of 70%. The proposed ADC is implemented with the standard CMOS 65 nm 1-poly 6-metal n-well process. The ADC achieves DNL/INL of?±?1.2LSB/?±?1.5LSB, ENOB of 10.3-b, power consumption of 31.2 μW, and Walden FoM of 2.7fJ/step.