A bipolar output voltage pulse transformer boost converter with charge pump assisted shunt regulator for thermoelectric energy harvesting

This system presents an energy harvesting system that generates bipolar output voltage (±1 V) based on a miniature 1:1 turn-ratio pulse transformer boost converter using sub-threshold level input voltage source. A shunt regulator is designed using six-transistor Schmitt-Trigger core to limit the boost converter output voltage. Another power stage, i.e. a fully integrated on-chip single-stage cross-coupled charge pump, then generates 3 V output from the unused extra output power of boost converter, which is shunted otherwise. The increased voltage headroom generated is instrumental for sensor, analog and RF circuits. Charge pump clock frequency is designed to adaptively tracking the input voltage, which is sensed using power-saving time-domain digital technique. Based on a standard CMOS 0.13-µm technology, chip measurement verified the operations of the boost converter, shunt regulator and bipolar charge pump prototypes, respectively. Simulations confirmed the full system operations. During start-up, the system only requires minimum start-up input voltage of 36 mV at input power of 5.8 µW.     

A transient enhanced DVS DC–DC converter based on state trajectory analysis

Dynamic voltage scaling (DVS) can effectively reduce energy consumption by dynamically varying the supply voltage of the system accordingly to the clock frequency. A new DVS-enabled DC–DC converter is presented in this paper. State trajectory is employed to analyze the transient features of PWM and PFM Buck converters. A novel transient enhancement circuit is designed to improve the transient response of the DVS-enabled Buck converter. To further expand the output voltage range of the converter, a current-starved voltage controlled delay line is proposed in the controller of DC–DC converter to obtain an ultra low voltage of 0.5 V. When the input voltage is 3.3 V, the output voltage of the converter can be dynamically regulated from 0.5 to 2.0 V. The output voltage tracking speed is less than 7.5 μs/V and the recovery speed is 33 μs/A for a load current step from 0.6 to 0.2 A at output voltage of 0.5 V. The chip area is 1.75 mm × 1.33 mm in a 0.18 μm standard CMOS process.     

A CMOS micro power switched-capacitor DC–DC step-up converter for indoor light energy harvesting applications

This paper presents a micro power light energy harvesting system for indoor environments. Light energy is collected by amorphous silicon photovoltaic (a-Si:H PV) cells, processed by a switched capacitor (SC) voltage doubler circuit with maximum power point tracking (MPPT), and finally stored in a large capacitor. The MPPT fractional open circuit voltage (V_OC) technique is implemented by an asynchronous state machine (ASM) that creates and dynamically adjusts the clock frequency of the step-up SC circuit, matching the input impedance of the SC circuit to the maximum power point condition of the PV cells. The ASM has a separate local power supply to make it robust against load variations. In order to reduce the area occupied by the SC circuit, while maintaining an acceptable efficiency value, the SC circuit uses MOSFET capacitors with a charge sharing scheme for the bottom plate parasitic capacitors. The circuit occupies an area of 0.31 mm² in a 130 nm CMOS technology. The system was designed in order to work under realistic indoor light intensities. Experimental results show that the proposed system, using PV cells with an area of 14 cm², is capable of starting-up from a 0 V condition, with an irradiance of only 0.32 W/m². After starting-up, the system requires an irradiance of only 0.18 W/m² (18 μW/cm²) to remain operating. The ASM circuit can operate correctly using a local power supply voltage of 453 mV, dissipating only 0.085 μW. These values are, to the best of the authors’ knowledge, the lowest reported in the literature. The maximum efficiency of the SC converter is 70.3 % for an input power of 48 μW, which is comparable with reported values from circuits operating at similar power levels.     

Frequency tunable low ripple and fast response on-chip DC–DC converter for DVFS

Dynamic voltage and frequency scaling (DVFS) is an efficient method to reduce the power consumption in system on-chip. To support DVFS, multiple supply voltages are generated based on different work load frequencies and currents using on-chip DC–DC voltage converter. In this paper a frequency tunable multiple output voltage switched capacitor based dc–dc converter is presented. An analog to digital converter and phase controller is used in the feedback to change the switching frequency and duty cycle of the converter. An input voltage of 1.8 V is converted to 0.6 and 0.8 V for low and high signal frequency respectively. The proposed 2-phase switched capacitor architecture with gain setting of 1:2 is designed with the 90 nm technology. An output ripple of 45 mV is observed and the maximum transient response time of the converter is 17.3 ns (= 58 MHz).     

Dual-output switched-capacitor DC–DC converter with pseudo-three-phase swap-and-cross control and amplitude modulation mechanism

This paper presents an inductorless dual-output switched-capacitor DC–DC converter employing pseudo-three-phase swap-and-cross control (PTPSCC) and an amplitude modulation mechanism (AMM). The AMM circuit scales the amplitudes of the driving signals for the switches according to the loading conditions in order to minimize switching losses. To reduce output ripples, average charge distribution, and improve regulation, the PTPSCC circuit continuously switches power transistors to deliver enough charge to the outputs by keeping at least one flying capacitor connected to each output. The switched capacitor DC–DC converter was implemented in a standard 0.18-μm 3.3-V CMOS process. Measurements were used to verify that the proposed converter provides dual independently regulated output voltages without cross regulation. The two outputs were regulated at 2.5 and 0.8 V with input ranges of 1.7–2 V. The maximum output loading was 100 mA for both outputs. A power efficiency of 90.5% was achieved at a maximum total output power of 330 mW with a switching frequency of 500 kHz, and a maximum power efficiency of 92.1% was achieved for a total output power of 210 mW. The maximal peak-to-peak output ripple voltages for the two outputs at 100 mA load currents were suppressed to below 26 and 20 mV, respectively.     

A 0.5-V low power analog front-end for heart-rate detector

This paper presents a low power analog front-end for heart-rate detector at a supply voltage of 0.5 V in 0.18 μm CMOS technology. A fully differential preamplifier is designed with a low power consumption of 300 nW. A 150 nW fourth order Switched-opamp switched capacitor bandpass filter is designed with passband 8–32 Hz. To digitize the analog signal, a low power second-order ΣΔ ADC is designed. The dynamic range and SNR of the converter are 46 dB and 54 dB respectively and it consumes a power of 125 nW. The overall front-end system including preamplifier, SO-SC bandpass filter, ΣΔ modulator and the biasing circuits are integrated and the total system consumes a power of 0.975 μW from 0.5 V supply.     

A novel maximum power point tracking technique for solar panels using a SEPIC or Cuk converter

A novel technique for efficiently extracting the maximum output power from a solar panel under varying meteorological conditions is presented. The methodology is based on connecting a pulse-width-modulated (PWM) DC/DC SEPIC or Cuk converter between a solar panel and a load or battery bus. The converter operates in discontinuous capacitor voltage mode whilst its input current is continuous. By modulating a small-signal sinusoidal perturbation into the duty cycle of the main switch and comparing the maximum variation in the input voltage and the voltage stress of the main switch, the maximum power point (MPP) of the panel can be located. The nominal duty cycle of the main switch in the converter is adjusted to a value, so that the input resistance of the converter is equal to the equivalent output resistance of the solar panel at the MPP. This approach ensures maximum power transfer under all conditions without using microprocessors for calculation. Detailed mathematical derivations of the MPP tracking technique are included. The tracking capability of the proposed technique has been verified experimentally with a 10-W solar panel at different insolation (incident solar radiation) levels and under large-signal insolation level changes.     

Wide input range,high-efficiency magnetic resonant wireless power receiver

This article presents a full-CMOS receiver for magnetic resonant wireless battery charging system. A wide-input range CMOS multi-mode active rectifier is proposed for a magnetic resonant wireless battery charging system. The configuration is automatically changed with respect to the magnitude of the input AC voltage. The output voltage of the multi-mode rectifier is sensed by a comparator. Furthermore, the configuration of the multi-mode rectifier is automatically selected by switches as original rectifier mode, one-stage voltage multiplier or two-stage voltage multiplier mode. As a result, a rectified DC output voltage is from 7.5 to 19 V for an input AC voltage of 5–20 V. This chip is implemented using 0.35 μm BCD technology with an active area of around 5 × 2.5 mm². When the magnitude of the input AC voltage is 10 V, the power conversion efficiency of the multi-mode active rectifier is about 94%.The efficiency of the receiver is about 60% when the distance between the transmitter and receiver is about 1 m.     

Equalization and pre-emphasis based LVDS transceiver

This work presents an area-efficient, low-power, high data rate low voltage differential signal (LVDS) transmitter and receiver with signal quality enhancing techniques. The proposed common mode feedback scheme significantly reduces the size of the LVDS transmitter by eliminating the use of area consuming passive resistor and capacitor used for close loop stability compensation. A preemphasis technique has been introduced to enhance the transmitter output’s signal quality without significantly increasing the power draw. On the receiver part, an equalization technique has also been introduced to further enhance signal quality, increases data rate and improved jitter with relatively low power consumption. The LVDS transmitter consumes 5.4 mA of current while driving an external 100 ohm resistor with an output voltage swing of 440 mV. The chip consumes an area of 0.044 mm². This LVDS receiver has an input common mode range from 0.1 to 1.6 V. It consumes 34 mW of power with a maximum data rate of 2 Gbps. It consumes an area of 0.147 mm² a jitter of 11.74 ps rms. A test chip is implemented using 0.18 μm CMOS process.     

A novel monolithic white LED driver with dual dimming mode

This paper presents a hysteretic-current-control LED driver with the dual dimming mode. This novel monolithic driver includes an output switch and a high-side output current sensing circuit using an external resistor to set the nominal average output current (I_OUTnom). By applying an external control signal to the DIM pin, it can alter flexibly the control mode between the analog (DC) and switching (PWM) dimming. In the DC dimming mode, when the input DC control voltage is adjusted from 0.5 to 2.5 V, the average output current can be changed from 20 to 100 % of the current I_OUTnom. While in the switching dimming mode, the output current is proportional to the duty cycle of the input switching signal and changed from about 0 to 100 % of the current I_OUTnom. The driver circuit has been verified in a 0.5 μm HVCMOS process and the die size is about 1.2 × 1.5 mm². This proposed driver can work in 8–40 V power supply, the maximum average output current is up to 1.0 A.     

A combined low power SAR capacitance-to-digital analog-to-digital converter for multisensory system

A combined successive approximation (SAR) capacitance-to-digital converter (CDC)/analog-to-digital converter (ADC) for biomedical multisensory system is presented in this paper. The two converters have same circuit blocks and can be exchanged by four switches. Capacitance or voltage from different sensing elements can be measured and converted to digital output directly. This single chip takes place of separated CDC and ADC so that the power consumption of the multisensory system is reduced. The asynchronous SAR circuit has low power and small area. A dynamic comparator with zero-static power is adopted. Switches are carefully designed to reduce the non-idealities of the converter. Several techniques, such as bootstrapped switches, bottom-plate sampling, dummy switches are used to improve the performance of the circuit. The CDC/ADC is fabricated in 0.18 μm CMOS process. Measurement results show that the ENOB of this 11 bits converter is 10.15 bits and its FOM is 45 fJ/conversion-step under 200 kHz sampling. The power consumption is 9.4 μW with 1.4 V power supply voltage and the core area is 0.1764 mm².     

An 80-V integrated boost converter for piezoelectric actuators in smartphones

A boost converter for piezoelectric actuator driving system in haptic smartphones is proposed and implemented using a 0.35 μm BCDMOS process. The designed boost converter generates extremely high output voltage from a low-voltage battery supply. The boost converter provides stable power for the piezoelectric actuator with the peak-current control technique. The minimum variation of the output ripple variation can be achieved by the designed current-sensing and peak-current control circuits. The supply voltage of the boost converter is 2.7–4.2 V and the maximum output voltage is up to 80 V. The complete piezoelectric actuator driving system consists of a serial interface, SRAM, and signal-shaping logic as well as the boost converter. It also includes the resistor-string digital-to-analog converter and high voltage piezoelectric actuator driver (PZ driver). The fabricated chip size is 2,100 × 2,200 μm, including bonding pads.     

A rail-to-rail differential quasi-digital converter for low-power applications

This paper presents an ultra low power differential voltage-to-frequency converter (dVFC) suitable to be used as a part of a multisensory interface in portable applications. The proposed dVFC has been designed in 1.2-V 0.18-μm CMOS technology, and it works properly over the whole differential input range (0.6 ± 0.6 V) providing an output frequency range of 0.0–0.9 MHz. The system has been tested for temperature variations from ?40 to +120 °C and supply voltage variations of up to 30 %, being the maximum linearity error in the worse case of 0.017 %. Simulations against common mode voltage variations show a deviation in the output frequency of 0.4 %. This dVFC has power consumption below 60 μW, and it includes an enable terminal that sets the system in a sleep mode (180 nW) while no conversion is request. The dVFC occupies an active area of 250 μm × 150 μm.     

8 Gbits/s inductorless transimpedance amplifier in 90 nm CMOS technology

This work presents the design and the measured performance of a 8 Gb/s transimpedance amplifier (TIA) fabricated in a 90 nm CMOS technology. The introduced TIA uses an inverter input stage followed by two common-source stages with a 1.5 kΩ feedback resistor. The TIA is followed by a single-ended to differential converter stage, a differential amplifier and a 50 Ω differential output driver to provide an interface to the measurement setup. The optical receiver shows a measured optical sensitivity of ?18.3 dBm for a bit error rate = 10^?9. A gain control circuitry is integrated with the TIA to increase its input photo-current dynamic range (DR) to 32 dB. The TIA has an input photo-current range from 12 to 500 μA without overloading. The stability is guaranteed over the whole DR. The optical receiver achieves a transimpedance gain of 72 dBΩ and 6 GHz bandwidth with 0.3 pF total input capacitance for the photodiode and input PAD. The TIA occupies 0.0036 mm² whereas the complete optical receiver occupies a chip area of 0.46 mm². The power consumption of the TIA is only 12 mW from a 1.2 V single supply voltage. The complete chip dissipates 60 mW where a 1.6 V supply is used for the output stages.     

Fuzzy Switching Technique Applied to PWM Boost Converter Operating in Mixed Conduction Mode for PV Systems

Due to the variation of the maximum power point (MPP) of photovoltaic (PV) generators with solar radiation and temperature, boost DC-DC converters placed between PV modules and inverters in grid-connected PV systems have to be controlled in a variable operating-point condition. In addition, inductor current dynamics changes suddenly when moving from continuous to discontinuous conduction mode. The previous difficulties make the design of reliable and fast control laws for the input voltage of boost converters complicated. The aim of this paper is to propose a control algorithm based on cascaded-loop control. The input voltage is controlled by the outer loop. The inductor current is controlled by an inner loop strategy which is able to perform in mixed conduction mode, owing to the fuzzy switching technique. Simulation and experimental results for a 10-kW boost converter show that the proposed strategy achieves an accurate and robust performance at every operating point, even if the inductor value varies in a wide range; thus, fast MPP tracking techniques can be implemented. An additional advantage is that constant switching frequency is achieved.     

A voltage mode buck DC–DC converter with automatic PWM/PSM mode switching by detecting the transient inductor current

This paper presents a voltage mode buck DC–DC converter that integrates pulse-width modulation (PWM) and pulse-skipping modulation (PSM) to achieve high efficiency under heavy and light load conditions, respectively. Automatic mode-switching is implemented simply by detecting the voltage drop of high-side power switch when it is on, which indicates the transient current flowing through the inductor. Unlike other methods based on average current sensing, the proposed auto-mode switching scheme is implemented based on voltage comparison and simple control logic circuit. In order to avoid unstable mode switching near the load condition boundary, the mode switching threshold voltage is set differently in PWM and PSM mode. Besides, a 16-cycle counter is also used to ensure correct detection of the change in the load condition and fast response of the converter. In addition, a dual-path error amplifier with clamp circuit is also adopted to realize loop compensation and ensure 100 % duty cycle operation. Fabricated in a 0.18-μm standard CMOS technology, the DC–DC converter is able to operate under supply voltage from 2.8 to 5.5 V with 3-MHz clock frequency. Measurement results show that the converter achieves a peak efficiency of 93 %, and an output voltage ripple of less than 40 mV, while the chip area is 1.02 mm².     

L, C and X band integrated synthetic aperture radar (SAR) receiver

An integrated receiver consisting of RF front ends, analog baseband (BB) chain with an analog to digital converter (ADC) for a synthetic aperture radar (SAR) implemented in 130 nm CMOS technology is presented in this paper. The circuits are integrated on a single chip with a size of 10.88 mm². The RF front end consists of three parallel signal channel intended for L, C and X-band of the SAR receiver. The BB is selectable between 50 and 160 MHz bandwidths through switches. The ADC has selectable modes of 5, 6, 7 and 8 bits via control switches. The receiver has a nominal gain of 40 and 37 dB and noise figure of 11 and 13.5 dB for 160 MHz BB filter at room temperature for L-band and C-band, respectively. The circuits, which use a 1.2 V supply voltage, dissipate maximum power of 650 mW with 50 MHz BB and 8 bit mode ADC, and maximum power of 800 mW with 160 MHz BB and 8 bit mode ADC.     

ZVS Buck-Boost LLC cascade converter with all soft switched switches

A Buck-Boost LLC cascade converter is proposed in this paper. In virtue of the Zero-Voltage-Switching (ZVS) modulation strategy for Buck-Boost circuit, all the switches can be soft switched with wide conversion range and full load range. By sharing one of the two bridge legs, the magnetizing current needed to realize the ZVS of switches decreases. Then, the power density and efficiency of the proposed converter increase. Theoretical analysis and characteristics of the proposed converter are presented and verified on a 210 V–400 V input 12 V/400 W output experimental prototype. The experimental results show that the proposed converter can achieve a peak efficiency of 95.6% at 1 MHz. The power density of the proposed converter is as high as 414 W/in³ with the help of GaN transistors and planar transformers.     

A novel MPPT circuit with 99.1% tracking accuracy for energy harvesting

A novel maximum power point tracking (MPPT) circuit based on Buck–Boost converter is presented for micro-power energy harvesting, which efficiently improves the power efficiency and robustness of system. The proposed MPPT uses the low-power analog multiplier and multi-outputs self-powered common-gate comparator to track the input power, and simplifies data calculation and structure greatly. The fast dynamic switching circuit and digital control circuit are introduced to enhance the adaptability and flexibility of system. The performance of whole converter was validated by the simulation results in a 65-nm CMOS process. The minimum starting voltage is 0.15 V. The peak output power is 40.5 µW, with a power loss of 14.1 µW. The peak power efficiency and peak tracking efficiency are 92.1 and 99.1%, respectively. The proposed MPPT has the advantages such as low power, high efficiency, fast tracking speed, simple structure.     

A DC–DC buck converter with load-regulation improvement using dual-path-feedback techniques

A DC–DC buck converter using dual-path-feedback techniques is proposed in this paper. The proposed converter is fabricated with TSMC 0.35 μm DPQM CMOS process. The structure of the proposed buck converter includes the voltage-feedback and current-feedback design to improve load regulation and achieve high efficiency. The experimental results show the maximum power efficiency is about 94 %. The load regulation is 6.22 (ppm/mA) when the load current changes from 0 to 300 mA. With a 3.6 V input power supply, the proposed buck converter provides an adjustable power output with a voltage range is from 1 to 3 V precisely.