高速电路中地弹噪声抑制的研究

研究了高速电路领域中的一类重要的电源完整性问题,即电源地平面之间激发的地弹噪声问题。地 弹噪声的存在严重破坏了电源/ 地平面的完整性,导致供电电压幅度的不稳定,严重之时甚至导致电路的误判。针 对这一问题,设计了一种超宽带电磁带隙结构。实验结果表明,这种电磁带隙结构可以在0. 5 ~5. 5GHz(11 倍频程) 频段内实现优于30dB 的噪声抑制能力。文章还探讨了带隙结构作为电源平面时信号传输的完整性。研究表明,如 果电路工作频率高达GHz 或更高,在电源/ 地平面采用这种带隙结构,可以有效地避免地弹噪声带来的影响,并保证 电源和信号的完整性。     

利用Allegro PCB PI进行电源完整性设计

在高速数字设计中,时钟频率的越来越高,同时芯片的规模也越来越大,以致电路的功耗越来越大,而供电电压却越来越低,由此导致信号完整性问题和电源完整性问题,正是高速电路设计中要解决的最重要问题。简要分析了高速电路设计中的电源完整性问题,介绍了利用EDA工具cadence中的Allegro PCB PI进行电源完整性分析和设计流程,并应用于工程实践,性能取得了明显改善。结合设计实例对此进行了说明和分析。     

一种基于传输线理论的新型GHz共模噪声抑制电路

基于传输线理论提出一种新型GHz宽阻带共模噪声抑制电路。利用双线传输线模型建立奇、偶模等效电路,在宽频带范围内准确预测了该电路结构的性能。实验结果表明:在1.9-4.5GHz频段内共模噪声抑制深度超-10dB,共模阻带相对带宽达81%;在dc-6GHz频段内差模插损小于3dB且差模信号群时延抖动较小,表明该结构可以很好地保证差模信号传输的信号完整性,性能优良。     

一款Ku 波段GaAs PHEMT 低噪声放大器

面向微波毫米波低噪声放大电路对高性能低噪声放大器件的需求,进行0. 15 μm 栅长GaAs PHEMT低噪声器件制备工艺的开发,在制备工艺中采用了欧姆特性优异的复合帽层欧姆接触、低寄生电容的介质空洞栅结构以及高击穿电压的双槽结构。在此基础上实现了一款性能优异的Ku 波段低噪声放大电路,电路在Ku 频段全频带(14 ~18 GHz)内实现了优良的性能,其噪声系数小于1. 3 dB,增益大于17 dB。电路采用5 V 电源供电,功耗为250 mW,芯片面积为2 mm×1. 6 mm;这款性能优异的Ku 频段低噪声放大器特别适用于高信噪比要求的卫星通信等应用。     

基板非圆过孔的信号完整性和电源完整性研究

随着科技的发展,半导体芯片的电源电压越来越小,电流越来越大,信号速度越来越高,从而导致电源完整性和信号完整性问题日益突出。对于一个电子系统来说,其电源完整性问题和互连的信号完整性问题来源包括芯片晶圆、封装、连接器、背板等,封装的电源完整性问题和信号完整性问题必须引起足够的重视。基板类封装中,过孔作为信号网络不同层之间的连接通道,其设计不当往往会造成严重的电源完整性问题和信号完整性问题。针对一种非圆形过孔应用于基板的电源完整性和信号完整性进行了研究,并对应用背景以及使用圆形过孔对其等效进行了探讨。     

一种低抖动、宽调节范围的带宽自适应CMOS锁相环

提出了一种低抖动、宽调节范围的带宽自适应CMOS锁相环.由于环路带宽可根据输入频率进行自动调节,电路性能可在整个工作频率范围内得到优化.为了进一步提高电路的抖动特性,在电荷泵电路中采用匹配技术,并在压控振荡器中应用电压-电压转换电路以减小压控振荡器的增益.芯片采用SMIC 0.35μm CMOS工艺加工.测试结果表明该锁相环电路可在200MHz～1.1GHz的输出频率范围内保持良好的抖动性能.     

一种新型差分脉宽控制环路的设计

设计了一种新型时钟稳定电路～差分脉宽控制电路.用参考电路产生参考电压,避免因采用环形振荡器等方法产生大的时钟抖动.同时,在控制电路部分用交叉耦合正反馈来调节时钟占空比.该电路采用0.18 μm工艺,电源电压为1.9 V,输入时钟占空比调节范围为25%～75%,时钟频率为2 GHz,时钟抖动小于200 fs.     

一种低抖动、宽调节范围的带宽自适应CMOS锁相环

提出了一种低抖动、宽调节范围的带宽自适应CMOS锁相环.由于环路带宽可根据输入频率进行自动调节,电路性能可在整个工作频率范围内得到优化.为了进一步提高电路的抖动特性,在电荷泵电路中采用匹配技术,并在压控振荡器中应用电压-电压转换电路以减小压控振荡器的增益.芯片采用SMIC 0.35μm CMOS工艺加工.测试结果表明该锁相环电路可在200MHz～1.1GHz的输出频率范围内保持良好的抖动性能.     

27.5GHz 0.2μm PHEMT1∶4静态分频器

描述了一种能运用于未来光传输系统SONETOC768的超高速1∶4静态分频器,其工作频率超过27GHz.该电路采用栅长为0.2μm,截止频率约为60GHz的砷化镓赝晶高电子迁移率晶体管工艺制作,采用共面波导作为电感实现了宽带阻抗匹配.通过采用推拉式有源跟随器,在没有增加功耗的情况下拓宽了频带.单端输入和差分信号输出的方式,为实际应用提供了便利.通过晶圆测试,在单端时钟输入的情况下,芯片的最高工作频率超过27GHz.测试所得到的波形均方根抖动小于820fs.芯片的面积是1.6mm×0.5mm,功耗为440mW.     

27.5GHz 0.2μm PHEMT 1:4静态分频器

描述了一种能运用于未来光传输系统SONET OC-768的超高速1∶4静态分频器,其工作频率超过27GHz.该电路采用栅长为0.2μm,截止频率约为60GHz的砷化镓赝晶高电子迁移率晶体管工艺制作,采用共面波导作为电感实现了宽带阻抗匹配.通过采用推拉式有源跟随器,在没有增加功耗的情况下拓宽了频带.单端输入和差分信号输出的方式,为实际应用提供了便利.通过晶圆测试,在单端时钟输入的情况下,芯片的最高工作频率超过27GHz.测试所得到的波形均方根抖动小于820fs.芯片的面积是1.6mm×0.5mm,功耗为440mW.     

Partial EBG Structure with DeCap for Ultra‐wideband Suppression of Simultaneous Switching Noise in a High‐Speed System

To supply a power distribution network with stable power in a high‐speed mixed mode system, simultaneous switching noise caused at the multilayer PCB and package structures needs to be sufficiently suppressed. The uniplanar compact electromagnetic bandgap (UC‐EBG) structure is well known as a promising solution to suppress the power noise and isolate noise‐sensitive analog/RF circuits from a noisy digital circuit. However, a typical UC‐EBG structure has several severe problems, such as a limitation in the stop band's lower cutoff frequency and signal quality degradation. To make up for the defects of a conventional EBG structure, a partially located EBG structure with decoupling capacitors is proposed in this paper as a means of both suppressing the power noise propagation and minimizing the effects of the perforated reference plane on the signal quality. The proposed structure is validated and investigated through simulation and measurement in both frequency and time domains.     

10Gbit／sX4小型可插拔并行光收发模块的研制

研制了一款基于系统级封装技术的低成本、收发一体和可带电热插拔的4通道小型可插拔（QSFP）光模块,采用850nm垂直腔面发射激光器（VCSEL）阵列及其驱动器作为发射端,光电探测器（PD）阵列及其跨阻放大器（TIA）作为接收端,通过光路无源对准,实现了低成本光互连。高速度、高密度封装下的瞬态同步开关噪声、芯片间电磁干扰...     

A 60-GHz-Band Analog Optical System-on-Package Transmitter for Fiber-Radio Communications

We developed an analog optical system-on-package (SoP) transmitter for a 60-GHz-band radio-over-fiber (RoF) link. The SoP transmitter consisted of an electroabsorption modulator, radio frequency amplifiers, and a bandpass filter. The 60-GHz RoF wireless link was prepared to measure the performance of the SoP transmitter. The transmission characteristics of 64-quadrature amplitude modulation (64-QAM) data of the 60-GHz RoF wireless link, including the SoP transmitter, were investigated by measuring the error vector magnitude (EVM) and signal-to-noise ratio (SNR) with a baseband frequency. The EVM of the 60-GHz RoF wireless link was between 2.25% and 2.80%, and the SNR was between 27.36 and 29.31 dB from 140 and 770 MHz, at input baseband power of -9 dBm. The noise figure had the minimum of 8.44 dB at 500 MHz. We successfully transmitted digital community antenna television (CATV) system signals through the 60-GHz RoF wireless link, including the SoP transmitter. Digital CATV signals of 86 channels could be transmitted through the 60-GHz RoF wireless link, and the total throughput was found to be 2.61 Gb/s.     

Wireless Dosimeter: System-on-Chip Versus System-in-Package for Biomedical and Space Applications

A new floating-gate (FG) MOSFET based wireless dosimeter system-in-package (SiP) is presented. This miniature and completely integrated wireless dosimeter SiP comprises a CMOS FG radiation sensor and transmitter (TX) in a low-temperature co-fired ceramic (LTCC) package. The design is very well suited to wireless transmission of radiation sensor data in radiotherapy and to Extra Vehicular Activity Radiation Monitoring (EVARM) in space. Two different solutions, namely system-on-chip (SoC) and SiP, are demonstrated. In the SoC, which is size and power efficient, the TX includes an on-chip loop antenna which also acts as the inductor for the VCO resonant tank circuit. The SiP solution has an LTCC antenna with optimized impedance to conjugate match the TX chip. The radiation sensor demonstrates a measured sensitivity of 5 mV/rad. The SoC module size is only 2 ${hbox {mm}}^{2}$, consumes 5.3 mW of power and delivers $-$0.9 dBm of radiated power, sufficient to communicate with a low noise receiver connected to an off-chip patch antenna placed 1.38 m away. The SiP design provides a larger communication range of 75 m at the cost of additional power consumption and size.      

一种系统级封装的ESD保护技术

介绍了一种系统级封装(SiP)的ESD保护技术。采用瞬态抑制二极管(TVS)构建合理的ESD电流泄放路径,实现了一种SiP的ESD保护电路。将片上核心芯片的抗ESD能力从HBM 2 000 V提升到8 000 V。SiP ESD保护技术相比片上ESD保护技术,抗ESD能力提升效果显著,缩短了开发周期。该技术兼容原芯片封装尺寸,可广泛应用于SiP类产品开发中。     

系统级封装(SiP)技术研究现状与发展趋势

系统级封装(System in Package,SiP)已经成为重要的先进封装和系统集成技术,是未来电子产品小型化和多功能化的重要技术路线,在微电子和电子制造领域具有广阔的应用市场和发展前景,发展也极为迅速。对目前SiP技术的研究现状和发展趋势进行了综述,重点关注了国际上半导体产业和重要的研究机构在SiP技术领域的研究和开发,对我国SiP技术的发展做了简单的回顾和展望。     

System-on-package: a broad perspective from system design to technology development

In this paper, we summarize and analyze main challenges towards system-on-package (SoP) integration with a broad perspective from system design to technology development. We see that the future SoP faces a main challenge of changed system architecture that will be different from today’s personal computer or PC-based systems. It is likely that communication-network based system architectures will be interesting to future SoP platforms. Second, we find that a major paradigm shift will occur in design methodology for SoP integration that emphasizes a coherent co-design of chip, package and system in a mixed signal environment and in combination with new issues such as virtual components integration. On the technology side, the major challenges will be power dissipation and system cooling, low-cost and thermal-matched high-density interconnect substrates, as well as low-cost passive components integration. Finally, we present some research examples that aim to cope with these new challenges on a strategic basis.     

高密度封装进展之三——SiP与SoC

哪种方式更能提高LST的附加值?是SiP(system in a package)还是SoC(system on a chip)?LSI厂家正对此进行激烈争论。作为系统集成的选择方式,LSI厂家一直集中力量致力于SoC的开发。但是LSI厂家发现,仅靠SoC这一条路线已不能满足用户的要求。目前,对于各大LSI厂家来说,要不要转换其发展资源的投入方向,需要当机立断。     

Intra- and inter-temperature measurement BIST for SiP module using digital frequency analyser circuit

A method and a novel circuitry for intra- and inter-chip temperature measurement in a system in a package (SiP) module is presented. The proposed built-in self-test (BiST) system for the SiP module features a newly proposed digital frequency analyser (DFA) that can be used to efficiently discern clock period differences of up to 1 ns. The full digital interface of the DFA enables power and area efficient temperature measurements in an SiP.