n-i-p型非晶硅太阳电池中p/ITO界面特性研究

采用射频等离子体增强化学气相沉积(RF-PECVD)技术,制备n-i-p型非晶硅(a-Si)太阳电池,采用反应热蒸发法制备ITO薄膜作为太阳电池的前电极。通过改变B2H6的掺杂浓度获得了不同晶化率的p层,详细研究了p层性能对p/ITO界面特性以及电池性能的影响。结果表明,在合适晶化率的p层上沉积ITO薄膜有利于优化p/ITO界面的接触特性,将其应用于n-i-p型a-Si太阳电池,能够显著改善电池的开路电压(Voc)和填充因子(FF),最终,在不锈钢(SS)衬底上获得了转换效率为6.57%的单结a-Si太阳电池。     

P-nc-si:H薄膜材料及在微晶硅薄膜太阳电池上应用

对RF PECVD技术沉积p nc Si:H薄膜材料进行了研究。随着功率的增大材料的晶化率增大。B的掺杂可以提高材料的电导率,同时会抑制材料的晶化,在纳米Si薄膜材料中B的掺杂效率很高,少量的B即可获得高的电导率,而对材料晶化影响不大。用比较高沉积功率和少量B的方法获得了高电导率、宽光学带隙和高晶化率的P型纳米Si薄膜材料(σ=0.7S/cm,Eopt>2.0eV)。将这种材料应用于微晶硅(μc Si)薄膜太阳能电池中,电池结构为:glass/SnO2/ZnO/p nc Si:H/I μC Si:H/n Si:H。首次获得效率η=4.2%的μC Si薄膜太阳能电池(Voc=0.399V,Jsc=20.56mA/cm2,FF=51.6%)。     

VHF-PECVD制备微晶硅材料及电池

采用VHF-PECVD技术制备了不同功率系列的微晶硅薄膜和电池,测试结果表明：制备的适用于微晶硅电池的有源层材料的暗电导和光敏性都在电池要求的参数范围内．低功率或高功率条件下,电池从n和p方向的喇曼测试结果是不同的,在晶化率方面材料和电池也有很大的差别,把相应的材料应用于电池上时,这一点很重要．采用VHFPECVD技术制备的微晶硅电池效率为5%,Voc=0.45V,Jsc=22mA/cm2,FF=50%,Area=0.253cm2．     

VHF-PECVD制备微晶硅材料及电池

采用VHF-PECVD技术制备了不同功率系列的微晶硅薄膜和电池,测试结果表明:制备的适用于微晶硅电池的有源层材料的暗电导和光敏性都在电池要求的参数范围内.低功率或高功率条件下,电池从n和p方向的喇曼测试结果是不同的,在晶化率方面材料和电池也有很大的差别,把相应的材料应用于电池上时,这一点很重要.采用VHF-PECVD技术制备的微晶硅电池效率为5%,Voc=0.45V,Jsc=22mA/cm2,FF=50%,Area=0.253cm2.     

NIP型非晶硅薄膜太阳能电池的研究

采用射频等离子体增强化学气相沉积(RF-PECVD)技术制备非晶硅(a-Si)NIP太阳能电池,其中电池的窗口层采用P型晶化硅薄膜,电池结构为Al/glass/SnO2/N(a-Si:H)/I(a-Si:H)/P(cryst-Si:H)/ITO/Al.为了使P型晶化硅薄膜能够在a-Si表面成功生长,电池制备过程中采用了H等离子体处理a-Si表面的方法.通过调节电池P层和N层厚度和H等离子体处理a-Si表面的时间,优化了太阳能电池的制备工艺.结果表明,使用H等离子体处理a-Si表面5 min,可以在a-Si表面获得高电导率的P型晶化硅薄膜,并且这种结构可以应用到电池上;当P型晶化硅层沉积时间12.5 min,N层沉积12 min,此种结构电池特性最好,效率达6.40%.通过调整P型晶化硅薄膜的结构特征,将能进一步改善电池的性能.     

CuxS背接触层制备及在碲化镉薄膜太阳电池中应用研究

本文采用化学水浴法沉积CuxS薄膜,通过改变Cu元素比例研究其对碲化镉电池效率的影响。研究表明化学水浴法沉积的CuxS是非晶的,采用适当退火条件可以使其晶化,随着退火温度的提高,薄膜变得致密且结晶明显。CuxS薄膜厚度对电池性能有很大的影响,结果表明,随着CuxS薄膜厚度增加,电池性能先增加后减少。薄膜厚度为75nm时,CdS/CdTe电池性能最佳,达到了最高转化效率(η)为12.19%,填充因子(FF)为68.82%,开路电压(Voc)为820mV。     

N-I-P 单结微晶硅太阳电池中N/I 与 I/P界面缓冲层的研究与优化

采用高压RF-PECVD技术制备了本征微晶硅薄膜和n-i-p结构微晶硅太阳电池。详细研究了n-i-p微晶硅太阳电池中n/i 和 i/p 缓冲层对太阳电池性能的影响。实验结果表明,提高n/i 界面晶化率以及在i/p 界面加入非晶缓冲层均有利于太阳电池性能的提高。通过优化界面缓冲层,微晶硅单结电池和非晶硅/微晶硅叠层电池的性能得到大幅度提高。     

RF-PECVD高速沉积优质过渡区微晶硅薄膜

利用13.56MHz射频等离子体增强化学气相沉积技术高速沉积非晶/微晶过渡区的微晶硅(μc-Si:H)薄膜.研究了沉积压力、射频功率、电极间距、氢稀释度等参数对沉积速率、电学性质等的影响.选择优化的沉积参数,在非晶到微晶的过渡区得到了沉积速率为0.3～0.4nm/s的μc-Si:H薄膜.薄膜的暗电导在10-7S/cm量级,光暗电导比近2个量级,电导激活能在0.52eV左右,薄膜结构致密,达到了器件级质量.     

RF-PECVD高速沉积优质过渡区微晶硅薄膜

利用13.56MHz射频等离子体增强化学气相沉积技术高速沉积非晶/微晶过渡区的微晶硅(μc-Si:H)薄膜.研究了沉积压力、射频功率、电极间距、氢稀释度等参数对沉积速率、电学性质等的影响.选择优化的沉积参数,在非晶到微晶的过渡区得到了沉积速率为0.3～0.4nm/s的μc-Si:H薄膜.薄膜的暗电导在10-7S/cm量级,光暗电导比近2个量级,电导激活能在0.52eV左右,薄膜结构致密,达到了器件级质量.     

RF-PECVD高速沉积优质过渡区微晶硅薄膜

利用13.56MHz射频等离子体增强化学气相沉积技术高速沉积非晶/微晶过渡区的微晶硅(μc-Si∶H)薄膜. 研究了沉积压力、射频功率、电极间距、氢稀释度等参数对沉积速率、电学性质等的影响. 选择优化的沉积参数，在非晶到微晶的过渡区得到了沉积速率为0.3～0.4nm/s的μc-Si∶H薄膜. 薄膜的暗电导在1e-7S/cm量级，光暗电导比近2个量级，电导激活能在0.52eV左右，薄膜结构致密，达到了器件级质量.     

Top-gate TFTs using 13.56 MHz PECVD microcrystalline silicon

Top-gate thin-film transistors (TFTs) with microcrystalline silicon (/spl mu/c-Si) channel layers deposited using standard 13.56 MHz plasma-enhanced chemical vapor deposition were fabricated at a maximum processing temperature of 250/spl deg/C. The TFTs employ amorphous silicon nitride (a-SiN) as the gate dielectric layer. The 80-nm-thick /spl mu/c-Si channel layer showed a dark conductivity of the order of 10/sup -7/ S/cm and a crystalline volume fraction of over 80%. The /spl mu/c-Si TFTs showed a field effect mobility of 0.85 cm/sup 2//V/spl middot/s, a threshold voltage of 4.8 V, a subthreshold slope of 1 V/dec, and an ON/OFF current ratio of /spl sim/10/sup 7/. More importantly, the TFTs were very stable under gate bias stress, offering promise for organic light-emitting display (OLED) applications.     

Polycrystalline silicon thin film transistors fabricated in various solid phase crystallized films deposited on glass substrates

In this work, we have characterized various types of polysilicon films, crystallized upon thermal annealing from films deposited by low pressure chemical vapor deposition in the amorphous phase and a mixed phase using silane or in the amorphous phase using disilane. Polysilicon thin film transistors (TFTs) were fabricated, at low processing temperatures, in these three types of films on high strain point Corning Code 1734 and 1735 glass substrates. Double layer films, with the bottom layer deposited in a mixed phase and the top in the amorphous phase, allowed TFT fabrication at a drastically reduced thermal budget; optimum values of thicknesses and deposition rates of the layers are reported for reducing the crystallization time and improving film quality. Optimum deposition conditions for TFT fabrication were also obtained for films deposited using disilane. The grain size distribution for all types of films was shown to be wider for a larger grain size. Fabricated TFTs exhibited field effect electron mobility values in the range of 20 to 50 cm²/V·s, subthreshold swings of about 0.5–1.5 V/dec and threshold voltage values of 2–4 V.     

Investigation of Co/SiC interface reaction

Interface reaction, phase transition, and composition were investigated for Co thin films on amorphous SiC films as a function of heat treatment (600～1000°C). Amorphous SiC layers were grown on (001) Si substrate by magnetron sputter deposition. The SiC layers had a 1:1 stoichiometric ratio of Si to C and an amorphous structure containing microcrystals. The interface reaction between a sputter-deposited Co (250Å thick) and amorphous SiC (2000Å thick) layer on a (001) Si substrate induced by vacuum annealing at temperatures of 600–1000°C was examined. Co₂Si was formed at 700°C as the first crystalline phase and CoSi at 800°C as the final stable phase of the Co/SiC interface reaction. This phase sequence of Co₂Si→CoSi was interpreted in terms of the effective heat of formation and the calculated ternary Co-Si-C phase diagram, and it was consistent with the experimental results. The high formation temperature of the first crystalline Co₂Si phase and no formation of a final stable CoSi₂ phase are discussed in comparison with Co/Si interface reaction and related to the binding energy of the reacting materials. In addition, the behavior of free carbon remaining after the Co/SiC reaction was investigated. This free carbon moved to the top of the reacted cobalt silicide/SiC layer.     

宽带隙ZnMgO的电学特性及其透明薄膜场效应晶体管

首次提出了用六方相晶体结构的宽带隙ZnMgO作为薄膜场效应晶体管（TFT）的沟道层，用立方相ZnMgO纳米晶体薄膜作为栅绝缘层，在实验中用透明的ITO导电玻璃作为衬底，通过连续沉积六方和立方相结构的纳米ZnMgO晶体薄膜，并通过光刻、电极工艺等，研制了透明的ZnO基TFT, TFT的电流开关比达到1E4，场效应迁移率为0.6cm2/(V·s).在偏压2.5MV/cm下漏电流为1E-8A.     

Silicon heterojunction solar cell: a new buffer Layer concept with low-temperature epitaxial silicon

Amorphous silicon/crystalline silicon heterojunction solar cells, deposited by the plasma-enhanced chemical vapor deposition (PECVD) technique, have been fabricated using different technologies to passivate defects at the heterointerface: without treatment, the insertion of a thin intrinsic amorphous layer or that of a thin intrinsic epitaxial layer. The open circuit voltage of heterojunction solar cells fabricated including an intrinsic amorphous buffer layer is strangely lower than in devices with no buffer layer. The structure of the amorphous buffer layer is investigated by high resolution transmission electron microscope observations. As an alternative to amorphous silicon, the insertion of a fully epitaxial silicon layer, deposited at low temperature with conventional PECVD technique in a hydrogen-silane gas mixture, was tested. Using the amorphous silicon/crystalline silicon (p a-Si/i epi-Si/n c-Si) heterojunction structure in solar cells, a 13.5% efficiency and a 605-mV open circuit voltage were achieved on flat Czochralski silicon substrates. These results demonstrate that epitaxial silicon can be successfully used to passivate interface defects, allowing for an open circuit voltage gain of more than 50 mV compared to cells with no buffer layer. In this paper, the actual structure of the amorphous silicon buffer layer used in heterojunction solar cells is discussed. We make the hypothesis that this buffer layer, commonly considered amorphous, is actually epitaxial.     

High-Performance barium titanate capacitors with double layer structure

High-performance barium titanate (B_aTiO₃) capacitors with excellent electrical and dielectric properties have been made by a two step deposition scheme using reactive rf magnetron sputtering. A novel double layer structure has been developed to reduce the pinholes and improve the electrical properties, such as higher dielectric constant, lower dissipation factor, higher breakdown fields and low leakage currents. Films deposited on a cooled substrate are amorphous whereas those deposited on a heated substrate are poly crystalline. Both polycrystalline and amorphous natures are verified by x-ray diffraction and scanning electron microscopy. Amorphous films have a low leakage current, a high breakdown voltage up to 2.5 x 10⁶ V/cm, and a dielectric constant less than 20. Polycrystalline films yield a high dielectric constant of 330. However, these films also have large leakage currents. The capacitors with the two layer structures,i.e. amorphous layer on top of polycrystal layer, have been shown to be much superior to those prepared by either polycrystal or amorphous layer alone for practical applications. The dielectric constant and breakdown voltage of capacitors with a double layer are found to be as high as 220 and 1.2 x 10⁶ V/cm, respectively. The leakage current is reduced to the same order as the amorphous films alone.     

Sub-500/spl deg/C solid-phase epitaxy of ultra-abrupt p/sup +/-silicon elevated contacts and diodes

A well-controlled low-temperature process, demonstrated from 350/spl deg/C to 500/spl deg/C, has been developed for epitaxially growing elevated contacts and near-ideal diode junctions of Al-doped Si in contact windows to the Si substrate. A physical-vapor-deposited (PVD) amorphous silicon layer is converted to monocrystalline silicon selectively in the contact windows by using a PVD aluminum layer as a transport medium. This is a solid-phase-epitaxy (SPE) process by which the grown Si is Al-doped to at least 10/sup 18/ cm/sup -3/. Contact resistivity below 10/sup -7/ /spl Omega//spl middot/cm/sup 2/ is achieved to both p/sup -/ and p/sup +/ bulk-silicon regions. The elevated contacts have also been employed to fabricate p/sup +/-n diodes and p/sup +/-n-p bipolar transistors, the electrical characterization of which indicates a practically defect-free epitaxy at the interface.     

GaN在Si(001)上的ECR等离子体增强MOCVD直接生长研究

研究了用电子回旋共振(ECR)等离子体增强金属有机物化学气相沉积(PEMOCVD)技术在Si(001)衬底上,低温(620～720℃)下GaN薄膜的直接外延生长及晶相结构.高分辨透射电镜(HRTEM)和X射线衍射(XRD)结果表明:在Si(001)衬底上外延出了高度c轴取向纤锌矿结构的GaN膜,但在GaN/Si(001)界面处自然形成了一层非晶层,其两个表面平坦而陡峭,厚度均匀(≈2nm).分析认为,在初始成核阶段N与Si之间反应所产生的这层SixNy非晶层使GaN的β相没有形成.XRD和原子力显微镜(AFM)结果表明,衬底表面的原位氢等离子体清洗,GaN初始成核及后续生长条件对GaN膜的晶体质量非常重要.     

GaN在Si(001)上的ECR等离子体增强MOCVD直接生长研究

研究了用电子回旋共振(ECR)等离子体增强金属有机物化学气相沉积(PEMOCVD)技术在Si(001)衬底上,低温(620～720℃)下GaN薄膜的直接外延生长及晶相结构.高分辨透射电镜(HRTEM)和X射线衍射(XRD)结果表明:在Si(001)衬底上外延出了高度c轴取向纤锌矿结构的GaN膜,但在GaN/Si(001)界面处自然形成了一层非晶层,其两个表面平坦而陡峭,厚度均匀(≈2nm).分析认为,在初始成核阶段N与Si之间反应所产生的这层SixNy非晶层使GaN的β相没有形成.XRD和原子力显微镜(AFM)结果表明,衬底表面的原位氢等离子体清洗,GaN初始成核及后续生长条件对GaN膜的晶体质量非常重要.