栅控二极管正向R-G电流对SOI体陷阱特征和硅膜结构的依赖性

使用半导体器件数值分析工具DESSISE-ISE,对侧向的P＋P－N＋栅控二极管的正向R-G电流对SOI体陷阱特征和硅膜结构的依赖性进行了详尽的研究．通过系统地改变硅膜体陷阱的密度和能级分布,得出了相应的P＋P－N＋栅控二极管的正向R-G电流的变化．同时,表征硅膜结构的参数如沟道掺杂和硅膜厚度的变化也使器件从部分耗尽向全耗尽方向转化,分析了这种转化对R-G电流大小和分布的影响．     

正向栅控二极管监测F- N电应力诱生的SOI- MOSFET界面陷阱

报道了正向栅控二极管 R- G电流法表征 F- N电应力诱生的 SOI- MOSFET界面陷阱的实验及其结果 .通过体接触的方式实现了实验要求的 SOI- MOSFET栅控二极管结构 .对于逐渐上升的累积应力时间 ,测量的栅控二极管电流显示出明显增加的 R- G电流峰值 .根据 SRH理论的相关公式 ,抽取出来的诱生界面陷阱密度是随累积应力时间的上升而呈幂指数的方式增加 ,指数为 0 .4.这一实验结果与文献先前报道的基本一致     

热载流子诱生MOSFET/SOI界面陷阱的正向栅控二极管技术表征

本文完成了热载流子诱生MOSFET/SOI界面陷阱正向栅控二极管技术表征的实验研究 .正向栅控二极管技术简单、准确 ,可以直接测得热载流子诱生的平均界面陷阱密度 ,从而表征器件的抗热载流子特性 .实验结果表明 :通过体接触方式测得的MOSFET/SOI栅控二极管R G电流峰可以直接给出诱生的界面陷阱密度 .抽取出来的热载流子诱生界面陷阱密度与累积应力时间呈幂指数关系 ,指数因子约为 0 787     

正向栅控二极管的 R- G电流直接表征 NMOSFET沟道 pocket或 halo注入区

使用半导体器件数值分析工具 DESSISE- ISE,对正向栅控二极管 R- G电流表征 NMOSFET沟道 pocket或halo注入区进行了详尽的研究 .数值分析表明 :由于栅控正向二极管界面态 R- G电流的特征 ,沟道工程 pocket或halo注入区的界面态会产生一个独立于本征沟道界面态 R- G电流特征峰的附加特征峰 .该峰的幅度对应于 pocket或 halo区的界面态大小 ,而其峰位置对应于 pocket或 halo区的有效表面浓度 .数值分析还进一步显示了该附加特征峰的幅度对 pocket或 halo区的界面态变化的敏感性和该峰的位置对 pocket或 halo区的有效表面浓度变化的敏感性 .根据提出的简单     

正向栅控二极管监测F-N电应力诱生的SOI-MOSFET界面陷阱

报道了正向栅控二极管R-G电流法表征F-N电应力诱生的SOI-MOSFET界面陷阱的实验及其结果．通过体接触的方式实现了实验要求的SOI-MOSFET栅控二极管结构．对于逐渐上升的累积应力时间,测量的栅控二极管电流显示出明显增加的R-G电流峰值．根据SRH理论的相关公式,抽取出来的诱生界面陷阱密度是随累积应力时间的上升而呈幂指数的方式增加,指数为0.4.这一实验结果与文献先前报道的基本一致．     

栅控二极管R-G电流法表征SOI-MOS器件埋氧层界面陷阱的敏感性分析

通过数值模拟手段 ,用归一化的方法研究了界面陷阱、硅膜厚度和沟道掺杂浓度对 R- G电流大小的影响规律 .结果表明 :无论在 FD还是在 PD SOI MOS器件中 ,界面陷阱密度是决定 R- G电流峰值的主要因素 ,硅膜厚度和沟道掺杂浓度的影响却因器件的类型而异 .为了精确地用 R- G电流峰值确定界面陷阱的大小 ,器件参数的影响也必须包括在模型之中     

热载流子诱生MOSFET／SOI界面陷阱的正向机控二极管技术表征

本文完成了热载流子诱生MOSFET/SOI界面陷阱正向栅控二极管技术表征的实验研究。正向栅控二极管技术简单、准确，可以直接测得热载流子诱生的平均界面陷阱密度，从而表征器件的抗热载流子特性。实验结果表明：通过体接触方式测得的MOSFET/SOI栅控二级管R-G电流峰可以直接给出诱生的界面陷阱密度。抽取出来的热载流子诱生界面陷阱密度与累积应力时间呈幂指数关系，指数因子约为0.787。     

新的正向栅控二极管技术分离热载流子应力诱生SOI NMOSFET界面陷阱和界面电荷的研究

报道了用新的正向栅控二极管技术分离热载流子应力诱生的SOI-MOSFET界面陷阱和界面电荷的理论和实验研究.理论分析表明:由于正向栅控二极管界面态R-G电流峰的特征,该峰的幅度正比于热载流子应力诱生的界面陷阱的大小,而该峰的位置的移动正比于热载流子应力诱生的界面电荷密度. 实验结果表明:前沟道的热载流子应力在前栅界面不仅诱生相当数量的界面陷阱,同样产生出很大的界面电荷.对于逐渐上升的累积应力时间,抽取出来的诱生界面陷阱和界面电荷密度呈相近似的幂指数方式增加,指数分别为为0.7 和0.85.     

新的正向栅控二极管技术分离热载流子应力诱生SOI NMOSFET界面陷阱和界面电荷的研究

报道了用新的正向栅控二极管技术分离热载流子应力诱生的SOI-MOSFET界面陷阱和界面电荷的理论和实验研究.理论分析表明:由于正向栅控二极管界面态R-G电流峰的特征,该峰的幅度正比于热载流子应力诱生的界面陷阱的大小,而该峰的位置的移动正比于热载流子应力诱生的界面电荷密度. 实验结果表明:前沟道的热载流子应力在前栅界面不仅诱生相当数量的界面陷阱,同样产生出很大的界面电荷.对于逐渐上升的累积应力时间,抽取出来的诱生界面陷阱和界面电荷密度呈相近似的幂指数方式增加,指数分别为为0.7 和0.85.     

用正向栅控二极管的方法对场效应晶体管的参数提取

本文用正向栅控二极管的方法来提取场效应晶体管的栅氧层厚度和体掺杂浓度,尤其是在这两个变量事先都未知的情况下进行提取。首先,用器件物理推导出了以栅氧层厚度、体掺杂浓度为参数的正向栅控二极管峰值电流。然后用ISE-Dessis模拟了不同栅氧层厚度和体衬底掺杂浓度下的产生复合电流峰值的特性,用于参数提取。模拟数据的结果与正向栅控二极管的方法显示出高度的一致性。     

Numerical Analysis of Characterized Back Interface Traps of SOI Devices by R-G Current

Characterized back interface traps of SOI devices by the Recombination\|Generation (R\|G) current has been analyzed numerically with an advanced semiconductor simulation tool,namely DESSIS\|ISE.The basis of the principle for the R\|G current's characterizing the back interface traps of SOI lateral p\++p\+-n\++ diode has been demonstrated.The dependence of R\|G current on interface trap characteristics has been examined,such as the state density,surface recombination velocity and the trap energy level.The R\|G current proves to be an effective tool for monitoring the back interface of SOI devices.     

Numerical Analysis of Characterized Back Interface Traps of SOI Devices by R-G Current

Characterized back interface traps of SOI devices by the Recombination-Generation (R-G) curren: has been analyzed numerically with an advanced semiconductor simulation tool,namely DESSiS-ISE. The basis of the principle for the R-G current's characterizing the back interface traps of SOI lateral p+p-n+ diode has been demonstrated. The dependence of R-G cur rent on interface trap characteristics has been examined, such as the state density, surface recombination velocity and the trap energy level. The R-G current proves to be an effective tool for monitoring the back interface of SOI devices.     

栅控二极管R-G电流法表征SOI-MOS器件埋氧层界面陷阱的敏感性分析

通过数值模拟手段,用归一化的方法研究了界面陷阱、硅膜厚度和沟道掺杂浓度对R-G电流大小的影响规律.结果表明:无论在FD还是在PD SOI MOS器件中,界面陷阱密度是决定R-G电流峰值的主要因素,硅膜厚度和沟道掺杂浓度的影响却因器件的类型而异.为了精确地用R-G电流峰值确定界面陷阱的大小,器件参数的影响也必须包括在模型之中.     

A 0.25-μm, 600-MHz, 1.5-V, fully depleted SOI CMOS 64-bitmicroprocessor

A 0.25-μm, four-layer-metal, 1.5-V, 600-MHz, fully depleted (FD) silicon-on-insulator (SOI) CMOS 64-bit ALPHA1 microprocessor integrating 9.66 million transistors on a 209-mm² silicon die has been developed leveraging the existing bulk design. FD-SOI technology is used because it has better immunity for dynamic leakage current than partially depleted SOI in high speed dynamic circuits without body contact. C-V characteristics of metal-oxide-silicon-oxide-silicon with and without source-drain junctions are described to explain the behavior of FD-SOI transistor. Race, speed, and dynamic stability have been simulated to reassure the circuit operation. Key process features are shallow trench isolation, 4-nm gate oxide, 30-nm co-silicide, 46-nm silicon film, and 200-nm buried oxide. The FD-SOI microprocessor runs 30% faster than that of bulk, and it passes the reliability and system test     

Body-contacted SOI MOSFET structure and its application to DRAM

A body-contacted (BC) SOI MOSFET structure without the floating-body effect is proposed and successfully demonstrated. The key idea of the proposed structure is that the field oxide does not consume the silicon film on buried oxide completely, so that the well contact can suppress the body potential increase in SOI MOSFET through the remaining silicon film between the field oxide and buried oxide. The junction capacitance of the proposed structure which ensures high-speed operation can also maintain that of the conventional thin-film SOI MOSFET at about 0.5 V. The measured device characteristics show the suppressed floating-body effect as expected. A 64 Mb SOI DRAM chip with the proposed BC-SOI structure has been also fabricated successfully. As compared with bulk MOSFET's, the proposed SOI MOSFET's have a unique degradation-rate coefficient that increases with increasing stress voltage and have better ESD susceptibility. In addition, it should be noted that the proposed SOI MOSFET's have a fully bulk CMOS compatible layout and process     

FD MOS SOI circuit to enhance the ratio of illuminated to dark current of a co-integrated a-Si:H photodiode

In this paper we first present the integration of amorphous silicon photodiodes with a fully depleted silicon on isolator (FD SOI) MOSFET circuit. Taking the advantage of the better subthreshold characteristic of FD SOI MOSFETs with respect to bulk devices, a very simple SOI circuit integrated with the amorphous silicon photodiode is presented to significantly improve the ratio of the circuit output current when the diode is illuminated to when it is not. The use of one additional reference source voltage to adjust the operating point of the photodiode, allows to obtain a very significant increase in this current ratio, much higher than what can be obtained using a simple diode. Circuit solutions used to amplify the diode current under illumination are usually more complicated and involve a capacitor or more transistors than the circuit we present. All the other properties of the photodetector, as its spectral characteristic and linear dependence of detection with light intensity are maintained. The circuit can also be used in conjunction with other circuits for further amplification and/or processing.     

Characterization of double gate MOSFETs fabricated by a simple method on a recrystallized silicon film

A simple process to fabricate double gate SOI MOSFET is proposed. The new device structure utilizes the bulk diffusion layer as the bottom gate. The active silicon film is formed by recrystallized amorphous silicon film using metal-induced-lateral-crystallization (MILC). While the active silicon film is not truly single crystal, the material and device characteristics show that the film is equivalent to single crystal SOI film with high defect density, like SOI wafers produced in early days. The fabricated double gate MOSFETs are characterized, which demonstrate excellent device characteristics with higher current drive and stronger immunity to short channel effects compared to the single gate devices.     

Improving bulk FinFET DC performance in comparison to SOI FinFET

The implementation of FinFET structure in bulk silicon wafers is very attractive due to low-cost technology and compatibility with standard bulk CMOS in comparison with silicon-on-insulator (SOI) FinFET. SOI and bulk FinFET were analyzed by a three-dimensional numerical device simulator. We have shown that bulk FinFET with source/drain-to-body (S/D) junctions shallower than gate-bottom has equal or better subthreshold performance than SOI FinFET. By reducing S/D junction depth, fin width scaling for suppression of short-channel-effects (SCEs) can be relaxed. On-state performance has also been examined and drain current difference between the SOI and bulk FinFET at higher body doping levels has been explained by investigating enhanced conduction in silicon-oxide interface corners. By keeping the body doping low and junctions shallower than the gate-bottom, bulk FinFET characteristics can be improved with no increase in process complexity and cost.