适用于OFDM UWB 系统的低功耗，大锁定范围注入锁定分频器

This paper describes a divide-by-two injection-locked frequency divider （ILFD） for frequency synthesizers as used in multiband orthogonal frequency division multiplexing （OFDM） ultra-wideband （UWB） systems. By means of dual-injection technique and other conventional tuning techniques, such as DCCA and varactor tuning, the divider demonstrates a wide locking range while consuming much less power. The chip was fabricated in the Jazz 0.18μm RF CMOS process. The measurement results show that the divider achieves a locking range of 4.85 GHz （6.23 to 11.08 GHz） at an input power of 8 dBm. The core circuit without the test buffer consumes only 3.7 mA from a 1.8 V power supply and has a die area of 0.38×0.28 mm^2. The wide locking range combined with low power consumption makes the ILFD suitable for its application in UWB systems.     

一种新型全集成高速双模分频器

A fully integrated 2n/2n+1 dual-modulus divider in GHz frequency range is presented.The improved structure can make all separated logic gates embed into correlative D flip–flops completely.In this way,the complex logic functions can be performed with a minimum number of devices and with maximum speed,so that lower power consumption and faster speed are obtained.In addition,the low-voltage bandgap reference needed by the frequency divider is specifically designed to provide a 1.0 V output.According to the design demand,the circuit is fabricated in 0.18 m standard CMOS process,and the measured results show that its operating frequency range is 1.1–2.5 GHz.The dual-modulus divider dissipates 1.1 m A from a 1.8 V power supply.The temperature coefficient of the reference voltage circuit is 8.3 ppm/°C when the temperature varies from40 to C125°C.By comparison,the dual-modulus divide designed in this paper can possess better performance and flexibility.     

应用于60-GHz无线通信的全差分锁相环频率综合器

A 40-GHz phase-locked loop(PLL) frequency synthesizer for 60-GHz wireless communication applications is presented. The electrical characteristics of the passive components in the VCO and LO buffers are accurately extracted with an electromagnetic simulator HFSS. A differential tuning technique is utilized in the voltage controlled oscillator(VCO) to achieve higher common-mode noise rejection and better phase noise performance. The VCO and the divider chain are powered by a 1.0 V supply while the phase-frequency detector(PFD)and the charge pump(CP) are powered by a 2.5 V supply to improve the linearity. The measurement results show that the total frequency locking range of the frequency synthesizer is from 37 to 41 GHz, and the phase noise from a 40 GHz carrier is –97.2 d Bc/Hz at 1 MHz offset. Implemented in 65 nm CMOS, the synthesizer consumes a DC power of 62 m W, including all the buffers.     

A wideband 0.13 μm CMOS LC-VCO for IMT-advanced and UWB applications

This paper presents an LC voltage controlled oscillator(VCO) in a dual-band frequency synthesizer for IMT-advanced and UWB applications.The switched current source,cross-coupled pair and noise filtering technique are adopted in this VCO design to improve the performance of the phase noise,power consumption,voltage amplitude,and tuning range.In order to achieve a wide tuning range,a reconfigurable LC tank with 4 bits switch control is adopted in the core circuit design.The size of the entire chip with pad is 1.11 0.98 mm2.The test results show that the current dissipation of the VCO at UWB and IMT-Advanced band is 3 mA and 4.5 mA in a 1.2 V supply.The tuning range of the designed VCO is 3.86-5.28 GHz and 3.14-3.88 GHz.The phase-noise at 1 MHz frequency offset from a 3.5 GHz and 4.2 GHz carrier is-123 dBc/Hz and-119 dBc/Hz,respectively.     

应用于K波段的宽锁定范围低功耗注入锁定三倍频器

This paper presents a wide locking range and low DC power injection-locked frequency tripler for Kband frequency synthesizers application. The proposed ILFT employs a variable current source to decouple the injection signal path and the bias current so that the third harmonic of the injection signal can be maximized to enlarge the locking range. Meanwhile, a 2-bit digital control capacity array is used to further increase the output frequency locking range. It is implemented in a 130-nm CMOS process and occupies a chip area of 0.7 0.8 mm2 without pads. The measured results show that the proposed ILFT can achieve a whole locking range from 18 to21 GHz under the input signal of 4 d Bm and the core circuit dissipates only 4 m W of DC power from a 0.8 V supply voltage. The measured phase noise degradation from that of the injection signal is only 10 d B at 1 MHz offset.     

A 5-GHz programmable frequency divider in 0.18-μm CMOS technology

正A 5-GHz CMOS programmable frequency divider whose modulus can be varied from 2403 to 2480 for 2.4-GHz ZigBee applications is presented.The divider based on a dual-modulus prescaler(DMP) and pulse-swallow counter is designed to reduce power consumption and chip area.Implemented in the 0.18-μm mixed-signal CMOS process,the divider operates over a wide range of 1-7.4 GHz with an input signal of 7.5 dBm;the programmable divider output phase noise is -125.3 dBc/Hz at an offset of 100 kHz.The core circuit without test buffer consumes 4.3 mA current from a 1.8 V power supply and occupies a chip area of approximately 0.015 mm~2.The experimental results indicate that the programmable divider works well for its application in frequency synthesizers.     

Harmonic-suppressed quadrature-input frequency divider for OFDM systems

A fully balanced harmonic-suppressed quadrature-input frequency divider is proposed. The frequency divider improves the quadrature phase accuracy at the output by using both input I/Q signals. Compared with conventional dividers, the circuit achieves an output I/Q phase sequence that is independent of the input I/Q phase sequence. Moreover, the third harmonic is effectively suppressed by employing a double degeneration technique. The design is fabricated in TSMC 0.13-μ m CMOS and operated at 1.2 V. While locked at 8.5 GHz, the proposed divider measures a maximum third harmonic rejection of 45 dB and a phase noise of -124 dBc/Hz at a 10 MHz offset. The circuit achieves a locking range of 15% while consuming a total current of 4.5 mA.     

Harmonic-suppressed quadrature-input frequency divider for OFDM systems

A fully balanced harmonic-suppressed quadrature-input frequency divider is proposed.The frequency divider improves the quadrature phase accuracy at the output by using both input I/Q signals.Compared with conventional dividers,the circuit achieves an output I/Q phase sequence that is independent of the input I/Q phase sequence.Moreover,the third harmonic is effectively suppressed by employing a double degeneration technique. The desig n is fabricated in TSMC 0.13-μm CMOS and operated at 1.2 V.While locked at 8.5 GHz,the proposed divider measures a maximum third harmonic rejection of 45 dB and a phase noise of-124 dBc/Hz at a 10 MHz offset.The circuit achieves a locking range of 15%while consuming a total current of 4.5 mA.     

A dual mode charge pump with adaptive output used in a class G audio power amplifier

A dual mode charge pump to produce an adaptive power supply for a class G audio power amplifier is presented.According to the amplitude of the input signals,the charge pump has two level output voltage rails available to save power.It operates both in current mode at high output load and in pulse frequency modulation (PFM) at light load to reduce the power dissipation.Also,dynamic adjustment of the power stage transistor size based on load current at the PFM mode is introduced to reduce the output voltage ripple and prevent the switching frequency from audio range.The prototype is implemented in 0.18μm 3.3 V CMOS technology.Experimental results show that the maximum power efficiency of the charge pump is 79.5%@ 0.5x mode and 83.6%@ lx mode.The output voltage ripple is less than 15 mV while providing 120 mA of the load current at PFM control and less than 18 mV while providing 300 mA of the load current at current mode control.An analytical model for ripple voltage and efficiency calculation of the proposed PFM control demonstrates reasonable agreement with measured results.     

采用PMOS底部电流源的低功耗电流自调整压控振荡器

This paper presents the design and implementation of a current self-adjusted VCO with low power consumption. In the proposed VCO, a bottom PMOS current source instead of a top one is adopted to decrease the tail noise. A current self-adjusted technique without additional external control signals is taken to ensure the VCO starts up in the whole band while keeping the power consumption relatively low. Meanwhile, the phase noise of the VCO at the low frequency （high Cvar） can be reduced by the technique. The circuit is implemented in 0.18 μm CMOS technology. The proposed VCO exhibits low power consumption of 〈1.6 mW at a 1.5 V supply voltage and a tuning range from 11.79 to 12.53 GHz. The measured phase noise at 1 MHz offset from the frequency 11.79 GHz is-104.7 dBc/Hz, and the corresponding FOM is -184.2 dBc/Hz.     

基于40 nm CMOS工艺的毫米波注入锁定分频器

设计了一款应用于60 GHz频率综合器的二分频注入锁定分频器。通过优化射频注入和直流偏置网络,降低了注入信号损耗,提高了注入效率;通过优化注入管和交叉管尺寸、减小寄生电容、降低振荡摆幅,提高了注入效率,降低了功耗;电磁仿真毫米波段电感,建立集总等效电路模型,实现了高感值、低串联电阻的差分电感的设计,提高了锁定范围。电路设计采用SMIC 40 nm 1P6M RF CMOS工艺,芯片核心面积为0.016 mm²。仿真结果表明,在0.8 V电源电压下,电路功耗为5.5 mW,工作频率范围为55.2~61.2 GHz,注入锁定范围为6.0 GHz,满足低功耗和宽锁定范围的要求,适用于毫米波段锁相环频率综合器。     

LC-tank divide-by-4 injection-locked frequency divider using the second-order harmonic feedback

A low voltage, wide locking range and operation range divide-by-4 injection-locked frequency divider (ILFD) is proposed in the paper and the ILFD was fabricated in the TSMC 90 nm RF-CMOS process. The divide-by-4 ILFD uses a cross-coupled voltage-controlled oscillator (VCO) with a parallel-tuned LC resonator and a three-transistor composite that acts as a linear and nonlinear mixer. At a drain-source bias of 0.6 V and at an incident power of 0 dBm, the operation range of the divide-by-4 ILFD is 5.3 GHz, from the incident frequency 21.1 GHz to 26.4 GHz, and the percentage of operation range is 22.31%. The locking range of the divide-by-4 ILFD is 1.4 GHz, from the incident frequency 21.1 GHz to 22.5 GHz, and the percentage of locking range is 6.42%. The core power consumption is 2.58 mW. The die area is 0.86 × 0.75 mm².     

LC-Tank Colpitts Injection-Locked Frequency Divider With Record Locking Range

A new wide locking range injection-locked frequency divider (ILFD) using a standard 0.18-$mu$ m CMOS process is presented. The ILFD is based on a differential voltage controlled oscillator (VCO) with two embedded injection metal oxide semiconductor field effect transistors (MOSFETs) for coupling external signal to the resonators. The new VCO is composed of two single-ended VCOs coupled with cross-coupled MOSFETs and a transformer. Measurement results show that at the supply voltage of 1.5 V, the divider's free-running frequency is tunable from 5.85 to 6.17 GHz, and at the incident power of 0 dBm the locking range is about 7.1 GHz (65.4%), from the incident frequency 7.3 to 14.4 GHz. The ILFD has a record locking range percentage among published divide-by-2 $LC$-tank ILFDs.      

A wide-locking range ÷3 injection-locked frequency divider using concurrent injection mechanisms

A new wide locking range divide-by-3 injection-locked frequency divider (ILFD) using a standard 0.18 μm CMOS process is presented. The ILFD uses two concurrent injection mechanisms with two independent push–push circuits to extend the locking range. It is realized with a cross-coupled n-core MOS LC-tank oscillator. The core power consumption of the ILFD core is 11.496 mW. The divider’s free-running oscillation frequency is tunable from 4.32 to 3.78 GHz by tuning the varactor’s control bias, and at the incident power of 0 dBm the maximum locking range is 3 GHz (25 %), from the incident frequency 10.5 to 13.5 GHz. The operation range is 3.6 GHz (30.76 %), from 9.9 to 13.5 GHz.     

Wide locking range divide-by-4 LC-tank injection-locked frequency divider using series-mixers

A novel wide locking range divide-by-4 injection-locked frequency divider (ILFD) is proposed in this paper and was implemented in the TSMC 0.18 μm 1P6 M CMOS process. The divide-by-4 ILFD uses a cross-coupled voltage-controlled oscillator with a parallel-tuned LC resonator and two mixers in series to serve as an injection device. At the drain-source bias of 0.8 V and at the incident power of 0 dBm, the locking range of the divide-by-4 is 1.7 GHz, from the incident frequency 10.3–12.0 GHz, and the percentage of locking range is 15.25 %. The core power consumption is 11.98 mW. At drain-source voltage of 0.9 V, the locking range of the divide-by-4 is 2 GHz, from the incident frequency 10.1–12.1 GHz, and the percentage is 18.0 %. At drain-source voltage of 1.0 V, the locking range is 2.2 GHz (20.0 %) from 9.9 to 12.1 GHz. The die area is 0.492 × 0.819 mm².     

Wide-locking range ÷3 series-tuned injection-locked frequency divider

A new wide locking range series-tuned (ST) divide-by-3 injection-locked frequency divider (ILFD) using a standard 0.18 μm CMOS process is presented. The ÷3 ILFD circuit is realized with a ST cross-coupled n-core MOS LC-tank oscillator. Two direct-injection MOSFETs in series are used as a frequency doubler and a dynamic linear mixer to widen the locking range. The power consumption of the ILFD core is 10.56 mW. The divider’s free-running frequency is tunable from 3.529 to 3.828 GHz by tuning the varactor’s control bias, and at the incident power of 0 dBm the maximum locking range is 2.3 GHz (21.6 %), from the incident frequency 9.5 to 11.8 GHz. The operation range is 2.5 GHz (23.7 %), from 9.3 to 11.8 GHz.     

A Low Voltage 0.35$mu$m CMOS FrequencyDivider With the Body Injection Technique

This letter proposes a new CMOS injection locked frequency divider (ILFD) fabricated in a 0.35 mum CMOS process. The ILFD circuit is realized with a cross-coupled CMOS LC-tank oscillator, and the injecticon is carried out through the bodies of cross- coupled transistors. The self-oscillating ILFD is injection-locked by second-(third-) harmonic input to obtain the division order of two (three). Measurement results show that at the supply voltage of 1.5 V and at the incident power of 10 dBm, the locking range is from the incident frequency 6.94 to 8.41 GHz in the divide-by-3 mode and the operation range is from the incident frequency 4.56 to 5.59 GHz in the divide-by-2 mode.     

A Ring-Oscillator-Based Wide Locking Range Frequency Divider

This letter proposes a wide locking range injection locked frequency divider (ILFD) and describes the operation principle of the ILFD. The circuit is made of a dual band two-stage differential complementery metal–oxide–semiconductor (CMOS) ring oscillator and is based on MOS switches directly coupled to the differential outputs of the ring oscillator. The divide-by-two ILFD can provide wide locking range and the measurement results show that at the supply voltage of 1.8-V, the divider free-running frequencies are 1.36GHz and 2.3GHz, and at the incident power of 0dBm, the locking range is about 1.75GHz from the incident frequency 1.9GHz to 3.65GHz at low band and 2.55GHz from 2.95GHz to 5.5GHz at high band.     

A low-voltage,low power divide-by-4 LC-tank injection-locked frequency divider

A low-voltage wide locking range injection-locked frequency divider (ILFD) using a standard 0.18?µm complementary metal-oxide-semiconductor process is presented. The ILFD is based on a differential LC VCO with one injection metal oxide semiconductor field effect transistor (MOSFET) for coupling external signals to the resonator. The low-voltage operation and wide locking range is obtained by boosting the gate voltage swing of the ILFD. Measurements show that at the supply voltage of 0.67?V, the divider's free-running frequency is tunable from 3.91 to 4.22?GHz, and the core power consumption is 1.87?mW. At the incident power of 0?dBm the divide-by-4 operation range is about 2?GHz (12.3%), from the incident frequency 15.3–17.3?GHz. The divide-by-2 locking range is about 5.1?GHz (77%), from the incident frequency 4.1–9.2?GHz.     

A Wide Locking Range Differential Colpitts Injection Locked Frequency Divider

This letter proposes a new wideband Colpitts injection locked frequency divider (ILFD) and describes the operation principle of the ILFD. The circuit consists of a differential CMOS LC-tank oscillator and a direct injection topology. The divide-by-two ILFD can provide wide locking range, and the measurement results show that at the supply voltage of 2.4 V, the tuning range of the free running ILFD is from 4.46 to 5.6 GHz, about 1.14 GHz, and the locking range of the ILFD is from 8.03 to 11.63 GHz, about 3.6 GHz, at the injection signal power of 0 dBm. The ILFD dissipates 19.92 mW at a supply voltage of 2.4 V and was fabricated in 1P6M 0.18 mum CMOS process. At the tuning voltage of 1.2 V, the measured phase noise of the free running ILFD is -110.8 dBc/Hz at 1 MHz offset frequency from 4.94 GHz and the phase noise of the locked ILFD is -135.4 dBc/Hz, while the input signal power is -4 dBm.