基于一种新的时空编码技术的片上总线的低延迟低能耗设计

在深亚微米设计中,降低能耗和传播延迟是片上全局总线所面对的两个最主要设计目标.本文提出了一种用于片上全局总线的时空编码方案,它既提高了性能又降低了峰值能耗和平均能耗.该编码方案利用空间总线倒相编码和时间编码电路技术的优点,在消除相邻连线上反相翻转的同时,减少了自翻转数和耦合翻转数.在应用该总线编码技术降低总线延时和能耗的设计中,给出了一种总线上插入中继驱动器的设计方法,以确定它们合适的尺寸和插入位置,使得在满足目标延时和翻转斜率要求的同时总线总的能耗最小.该方法可用来为各种编码技术获得翻转斜率约束下的总线能耗与延时的优化折中.     

一种低延迟低功耗的片上全局互连方法

提出了一种用于片上全局互连的混合插入方法.该方法利用中继驱动器和低摆幅差分信号电路在驱动不同长度连线时的优点,将它们混合插入到连线的合适位置,从而降低互连的延时和功耗.模拟结果表明,该方法与已有方法相比在延时、能耗、能耗延时积以及面积等方面都获得了一定程度的改善.     

一种低延迟低功耗的片上全局互连方法

提出了一种用于片上全局互连的混合插入方法. 该方法利用中继驱动器和低摆幅差分信号电路在驱动不同长度连线时的优点，将它们混合插入到连线的合适位置，从而降低互连的延时和功耗. 模拟结果表明，该方法与已有方法相比在延时、能耗、能耗延时积以及面积等方面都获得了一定程度的改善.     

一种抑制总线串扰的自适应时空编码方法

片上总线互连线间逐步增强的线间耦合效应加剧了总线信号串扰.本文根据互连线串扰模型,提出先传送奇数位信息,再传送偶数位信息,双时钟周期发送恶性串扰总线数据的自适应时间编码方法.在消除恶性串扰的同时,减小了总线自翻转能耗.并结合码本编码,获得一种自适应时空编码方法.仿真结果显示该方法的时间节省率达到30%以上,能耗节省率为4%～38%.对于32位数据总线,该方法仅需6根冗余线.     

片上网络中降低信号串扰的方法

NOC（片上网络）的体系结构解决了SOC（片上系统）在大规模集成IP核时面临的一些难题,但其串扰问题对电路性能的影响也越来越明显。基于DSM（深亚微米）下的总线模型,分析了信号串扰引起的总线延时问题,同时比较了3种减小总线串扰的编码方案。并采用0．13μmCMOS工艺对性能较优的DAP编码方案进行了电路仿真,得到了不同长度和宽度下的总线延时。结果表明,采用减少信号串扰的编码方法可以有效地降低总线的串扰,减少信号延时,这一效果当总线较宽或走线较长时尤其明显,同时也证明了0．13μmCMOS工艺下电路仿真结果与理论计算结果的一致性。     

一种抑制同步开关噪声的改进总线翻转编码方法

提出了一种改进总线翻转编码方法,用于抑制高速集成电路系统中的同步开关噪声.该方法可以显著减少总线平均翻转比特位数,同时尽可能使总线相邻位保持奇模传输,有利于改善信号完整性.利用FPGA实现了提出的改进总线翻转编码模块.物理实验表明,相对总线翻转编码,该方法以功耗稍有增加的代价,可取得平均翻转数量减少15.17%、电源波动噪声减小22.34%的编码增益.     

G.718音频编码器核心层的一种低延时编码方案

语音编码器不仅要求提供高质量的语音,同时还要具有较低的编解码延时。为了降低G.718编码器核心层的延时,提出了一种帧长为5 ms的低延时编码方案,该方案将编码延时降低了25 ms。主客观语音评测结果表明,该方案具有接近G.718核心层的重建语音质量。     

一种基于频繁值和位变换感知的数据总线节能方法

深亚微米工艺下,片上数据总线能耗占嵌入式多核芯片能耗的比重越来越大.FV-MSB（Frequent Value-Most Significant Bits）方法降低了片外数据总线的能耗,但对于非频繁值和频繁高位值的低位部分未做处理,为进一步降低片上总线动态能耗,设计了一种基于频繁值和位变换感知的片上总线节能方法.利用频繁值和对位变换数的感知选择编码方式,大幅减少了数据总线上的位变换,有效降低了总线动态能耗.70nm工艺下,仿真实验结果显示,本文的方法最大节能比例可达17.76%,平均节能比例达16.91%,较FV-MSB方法使节能比例提高了6.28%.并且节能比例随λ的变化趋势表明本方法在未来工艺尺寸缩小时仍能发挥作用.     

低翻转率的SoC总线组合编码算法

为降低SoC总线功耗，避开现有总线编码技术在应用上的局限，提出了一种SoC总线编码算法。算法基于总线上IP可复用的观点，采用分组BI码和TO码各自的优点，在维持SoC总线功能基本不变的同时，减少数据线和地址线的电平翻转。最后的实验结果表明：组合编码算法可以将SoC总线的平均功耗下降7．41％，是一种有效且适用于SoC总线的低功耗算法。     

一种低功耗CPU卡的设计

地址总线的功耗是整个CPU卡电路系统功耗的重要来源.降低地址总线上的翻转率可以有效降低整个系统的功耗.文章在分析CMOS电路功耗和几种总线编码的基础上,提出了一种改进的T0-BI编码,并将此种编码应用于CPU卡用芯片的设计.结果表明,采用此种编码可以有效地降低CPU卡电路的功耗.     

Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses

We propose various low-latency spatial encoder circuits based on bus-invert coding for reducing peak energy and current in on-chip buses with minimum penalty on total latency. The encoders are implemented in dual-rail domino logic with interfaces for static inputs and static buses. A spatial and temporally encoded dynamic bus technique is also proposed for higher performance targets. Comparisons to standard on-chip buses of various lengths with optimal repeater configurations at the 130-nm node show the energy-delay and peak current-delay design space in which the different encoder circuits are beneficial. A 9-mm spatially encoded static bus exhibits peak energy gains beyond that achievable through repeater optimization for a single-cycle operation at 1 GHz, with delay and energy overhead of the encoding included. For throughput-constrained buses, the spatially encoded static bus can provide up to 31% reduction in peak energy, while the spatially and temporally encoded dynamic bus yields peak current reductions of more than 50% for all bus lengths. The encoder circuits show good scaling properties since the performance penalty from encoding decreases with scaled interconnects.     

Adaptive low-power address encoding techniques using self-organizing lists

Off-chip bus transitions are a major source of power dissipation for embedded systems. In this paper, new adaptive encoding schemes are proposed that significantly reduce transition activity on data and multiplexed address buses. These adaptive techniques are based on self-organizing lists to achieve reduction in transition activity by exploiting the spatial and temporal locality of the addresses. Also the proposed techniques do not require any extra bit lines and have minimal delay overhead. The techniques are evaluated for efficiency using a wide variety of application programs including SPEC 95 benchmark set. Unlike previous approaches that focus on instruction address buses, experiments demonstrate significant reduction in transition activity of up to 54% in data address buses and up to 59% in multiplexed address buses. The average reductions are twice those obtained using current schemes on a data address bus and more than twice those obtained on a multiplexed address bus.     

Reducing Interconnect Delay Uncertainty via Hybrid Polarity Repeater Insertion

Capacitive crosstalk between adjacent signal wires has significant effect on performance and delay uncertainty of point-to-point on-chip buses in deep submicrometer (DSM) VLSI technologies. We propose a hybrid polarity repeater insertion technique that combines inverting and non-inverting repeater insertion to achieve constant average effective coupling capacitance per wire transition for all possible switching patterns. Theoretical analysis shows the superiority of the proposed method in terms of performance and delay uncertainty compared to conventional and staggered repeater insertion methods. Simulations at the 90-nm node on semi-global METAL5 layer show around 25% reduction in worst case delay and around 86% delay uncertainty minimization compared to standard bus with optimal repeater configuration. The reduction in worst case capacitive coupling reduces peak energy which is a critical factor for thermal regulation and packaging. Isodelay comparisons with standard bus show that the proposed technique achieves considerable reduction in total buffers area, which in turn reduces average energy and peak current. Comparisons with staggered repeater which is one of the simplest and most effective crosstalk reduction techniques in the literature show that hybrid polarity repeater offers higher performance, less delay uncertainty, and reduced sensitivity to repeater placement variation.      

Coding for system-on-chip networks: a unified framework

Global buses in deep-submicron (DSM) system-on-chip designs consume significant amounts of power, have large propagation delays, and are susceptible to errors due to DSM noise. Coding schemes exist that tackle these problems individually. In this paper, we present a coding framework derived from a communication-theoretic view of a DSM bus to jointly address power, delay, and reliability. In this framework, the data is first passed through a nonlinear source coder that reduces self and coupling transition activity and imposes a constraint on the peak coupling transitions on the bus. Next, a linear error control coder adds redundancy to enable error detection and correction. The framework is employed to efficiently combine existing codes and to derive novel codes that span a wide range of tradeoffs between bus delay, codec latency, power, area, and reliability. Using simulation results in 0.13-/spl mu/m CMOS technology, we show that coding is a better alternative to repeater insertion for delay reduction as it reduces power dissipation at the same time. For a 10-mm 4-bit bus, we show that a bus employing the proposed codes achieves up to 2.17/spl times/ speed-up and 33% energy savings over a bus employing Hamming code. For a 10-mm 32-bit bus, we show that 1.7/spl times/ speed-up and 27% reduction in energy are achievable over an uncoded bus by employing low-swing signaling without any loss in reliability.     

Simultaneously optimizing crosstalk and power for instruction bus coupling capacitance using wire pairing

The use of deep-submicrometer (DSM) technology increases the capacitive coupling between adjacent wires leading to severe crosstalk noise, which causes power dissipation and may also lead to malfunction of a chip. In this paper, we present a technique that reduces crosstalk noise on instruction buses. While previous research focuses primarily on address buses, little work can be applied efficiently to instruction buses. This is due to the complex transition behavior of instruction streams. Based on instruction sequence profiling, we exploit an architecture that encodes pairs of bus wires and permute them in order to optimize power and noise. A close to optimal architecture configuration is obtained using a genetic algorithm. Unlike previous bus encoding approaches, crosstalk reduction can be balanced with delay and area overhead. Moreover, if delay (or area) is most critical, our architecture can be tailored to add nearly no overhead to the design. For our experiments, we used instruction bus traces obtained from 12 SPEC2000 benchmark programs. The results show that our approach can reduce crosstalk up to 50.79% and power consumption up to 55% on instruction buses.     

Maximal Delay Reduction for RLC-Based Multi-Source Multi-Sink Bus with Repeater Insertion

Signal propagation delay on a multi-source multi-sink bidirectional bus has a dominant effect on high-performance chips. This work presents a novel greedy algorithm that minimizes the critical propagation delay of an RLC-based bus. Based on the topology of a multi-source multi-sink bus and the RLC delay model, the proposed algorithm inserts signal repeaters into the critical path of the RLC-based bus and adjusts their sizes to minimize the maximal propagation delay. This procedure is repeated until no additional improvement is needed. Several buses with various topologies are tested using the proposed algorithm in deep submicron technologies. Experimentally, the critical delay in an RLC-based bus can be reduced dramatically by up to 62.4% with inserted repeater sizes of 24 and execution time of 1.65 s on average. Moreover, average delay reduction, repeater sizes, and running time for 0.18 μm technology are 5.8%, 6.4%, and 26.2%, respectively, better than those of 0.35 μm. Additionally, the topologies of all of the RLC-based buses with inserted repeaters in deep submicron technologies are simulated using HSPICE. The error ratio in the critical delay of a bus with inserted repeaters determined by comparison with HSPICE is 2.7% on average. The proposed algorithm is simple and extremely practical.     

Efficient RC low-power bus encoding methods for crosstalk reduction

In on-chip buses, the RC crosstalk effect leads to serious problems, such as wire propagation delay and dynamic power dissipation. This paper presents two efficient bus-coding methods. The proposed methods simultaneously reduce more dynamic power dissipation and wire propagation delay than existing bus encoding methods. Our methods also reduce more total power consumption than other encoding methods. Simulation results show that the proposed method I reduces coupling activity by 26.7-38.2% and switching activity by 3.7%-7% on 8-bit to 32-bit data buses, respectively. The proposed method II reduces coupling activity by 27.5-39.1% and switching activity by 5.3-9% on 8-bit to 32-bit data buses, respectively. Both the proposed methods reduce dynamic power by 23.9-35.3% on 8-bit to 32-bit data buses and total propagation delay by up to 30.7-44.6% on 32-bit data buses, and eliminate the Type-4 coupling. Our methods also reduce total power consumption by 23.6-33.9%, 23.9-34.3%, and 24.1-34.6% on 8-bit to 32-bit data buses with the 0.18, 0.13, and 0.09 μm technologies, respectively.     

A transition-encoded dynamic bus technique for high-performance interconnects

This paper describes a transition-encoded dynamic bus technique that enables on-chip interconnect delay reduction while maintaining the robustness and switching energy behavior of a static bus. Efficient circuits, designed for a drop-in replacement, enable significant delay and peak-current reduction even for short-length buses, while obtaining energy savings at aggressive delay targets. On a 180-nm 32-bit microprocessor, 79% of all global buses exhibit 10%-35% performance improvement using this technique.     

片上网络的互连问题及解决措施综述

在大规模集成电路工艺的深亚微米时代,片上网络（NoC）互连总线遭遇了来自三个方面的威胁：功耗、传输延时、可靠性,它们已经成为限制NoC性能提高的瓶颈。鉴于总线编码的灵活性和综合处理能力,本文首先分析了多种分别针对功耗、延时、可靠性问题的总线编码处理方案,最后介绍了一种统一的总线编码框架来综合处理这三方面的挑战。