Humidity sensitive organic field effect transistor

This paper reports the experimental results for humidity dependent properties of organic field effect transistor. The organic field effect transistor was fabricated on thoroughly cleaned glass substrate, in which the junction between metal gate and organic channel plays the role of gate dielectric. The thin films of organic semiconductor copper phthalocynanine (CuPc) and semitransparent Al were deposited in sequence by vacuum thermal evaporation on the glass substrate with preliminary deposited Ag source and drain electrodes. Output and transfer characteristics of the fabricated device were performed. The effect of humidity on the drain current, drain current-drain voltage relationship, and threshold voltage have been investigated. It was observed that humidity has strong effect on the characteristics of organic field effect transistor (OFET).     

Degradation of short-channel MOSFET's under constant current stress across gate and drain

We have employed a technique of constant current stress between the gate and drain of a MOS transistor to study the degradation of the threshold voltage, transconductance, and substrate current characteristics of the transistor. From the transistor characteristics, we propose that the degradation mechanism is a combined effect of trapping of holes in the gate oxide created by impact ionization due to the high electric field (> 8 MV/cm) across the oxide, and electron trapping phenomena. The degradation characteristics of the transistor under this constant current stress are quite similar to that observed normally due to the injection of hot electrons in the gate oxide when the transistor is biased in "ON" condition and the gate and drain voltages are selected to produce maximum substrate current.     

Stacked pentacene layer organic thin-film transistors with improvedcharacteristics

Using two layers of pentacene deposited at different substrate temperatures as the active material, we have fabricated photolithographically defined organic thin-film transistors (OTFTs) with improved field-effect mobility and subthreshold slope. These devices use photolithographically defined gold source and drain electrodes and octadecyltrichlorosilane-treated silicon dioxide gate dielectric. The devices have field-effect mobility as large as 1.5 cm²/V-s, on/off current ratio larger than 10⁸, near zero threshold voltage, and subthreshold slope less than 1.6 V per decade. To our knowledge, this is the largest field-effect mobility and smallest subthreshold slope yet reported for any organic transistor, and the first time both of these important characteristics have been obtained for a single device     

On-Resistance Modulation of High Voltage GaN HEMT on Sapphire Substrate Under High Applied Voltage

The 620-V/1.4-A GaN high-electron mobility transistors on sapphire substrate were fabricated and the ON-resistance modulations caused by current collapse phenomena were measured under high applied voltage. Since the fabricated devices had insulating substrates, no field-plate (FP) effect was expected and the ON-resistance increases of these devices were larger than those on an n-SiC substrate even with the same source-FP structure. The dual-FP structure, which was a combination of gate FP and source FP, was effective in suppressing the ON -resistance increase due to minimization of the gate-edge electric field concentration. The ON-resistance after the applied voltage of 250 V decreased by twice that at low drain voltage by the dual-FP structure. Gallium nitride (GaN), high-electron mobility transistor (HEMT), high voltage, power semiconductor device.     

A high-performance polycrystalline silicon thin film transistorwith a silicon nitride gate insulator

We have fabricated a high performance polycrystalline silicon (poly-Si) thin film transistor (TFT) with a silicon-nitride (SiN_x ) gate insulator using three stacked layers: very thin laser of hydrogenated amorphous silicon (a-Si:H), SiN_x and laser annealed poly-Si. After patterning thin a-Si:H/SiN_x layers, gate, and source/drain regions were ion-doped and then Ni layer was deposited. This structure was annealed at 250°C to form a NiSi silicide phase. The low resistive Ni silicides were introduced as gate/source/drain electrodes in order to reduce the process steps. The poly-Si with a grain size of 250 nm and low resistance n⁺ poly-Si for ohmic contact were introduced to achieve a high performance TFT. The fabricated poly-Si TFT exhibited a field effect mobility of 262 cm²/Vs and a threshold voltage of 1 V     

基于HfO2栅介质的Ga2O3 MOSFET器件研制

采用金属有机化学气相沉积(MOCVD)方法在(010) Fe掺杂半绝缘Ga2O3同质衬底上外延得到n型β-Ga2O3薄膜材料,材料结构包括400 nm的非故意掺杂Ga2O3缓冲层和40 nm的Si掺杂Ga2O3沟道层.基于掺杂浓度为2.0×1018 cm-3的n型β-Ga2O3薄膜材料,采用原子层沉积的25 nm的HfO2作为栅下绝缘介质层,研制出Ga2O3金属氧化物半导体场效应晶体管(MOSFET).器件展示出良好的电学特性,在栅偏压为8V时,漏源饱和电流密度达到42 mA/mm,器件的峰值跨导约为3.8 mS/mm,漏源电流开关比达到108.此外,器件的三端关态击穿电压为113 V.采用场板结构并结合n型Ga2O3沟道层结构优化设计能进一步提升器件饱和电流和击穿电压等电学特性.     

基于肖特基接触的碳纳米管场效应晶体管

由于具有独特的一维纳米结构、稳定的化学特性和优异的电学性能,单壁碳纳米管被认为是制作高性能电子器件以及下一代纳米电路的理想材料,作为新型基础电子元件的一种,碳纳米管场效应晶体管一直是研究的热点。研究了一种基于非对称肖特基接触的碳纳米管场效应晶体管,金属钯与金属铝分别作为电极材料制作出的碳纳米管场效应晶体管分别表现出p型和n型的导通特性,当这两种金属分别作为源、漏电极制作在单根半导体性单壁碳纳米管的两端时,便构成了非对称肖特基接触结构碳纳米管场效应晶体管。器件表现出了优良的整流特性,整流比达到103,在栅压的调控下,正向电流的开关比接近103。     

Low temperature processed mosfet's using laser recrystallized polycrystalline silicon films

An n-channel MOS transistor was fabricated on a laser recrystallized polycrystalline silicon film at temperatures below 630°C. The gate oxide was sputter deposited at 200°C. Lasers were used for substrate recrystallization, implantation damage annealing and dopant drive-in. An electron field effect mobility higher than 100 cm²/V · sec. was observed on the finished transistors. With 10 V applied to the gate of the transistors for 2 hr, less than a 20 mV shift in threshold voltage was observed.     

Top Contact Pentacene Organic Thin Film Field Effect Transistors

Using pentacene as an active material, the organic thin film transistors were fabricated on Si_(3)N_(4)/p-Si substrates by using RF-magnetron sputtered amorphous aluminium as the gate electrode contact, and using highly doped Si as the gate electrode and substrate with plasma-enhanced chemical vapor deposited (PECVD) silicon nitride as gate dielectric. Pentacene thin films were deposited by thermal evaporation on dielectrics as the active layer, then RF-magnetron sputtered amorphous aluminium was used as the source and drain contacts. Measurement results show that field effect mobility and threshold voltage are 0.043 cm~2/(V·s) and 12.6 V, respectively, and on-off current ratio is nearly 1×10~(3).     

A novel field effect transistor with dielectric polymer gel

A novel organic-field effect transistor (OFET) has been fabricated. This device is original in the sense that it can be produced in ambient conditions with facile and cost-effective methods. Experimental results surprisingly revealed a high mobility value at the order of 0.38 cm²/Vs, and the gate voltage is also found to be lower than 1 V. The device exhibited excellent transistor characteristics at low voltages. Threshold voltage is around 0.26 V with 10³ on/off ratio. The device design is based on high effective capacitance value of a polymer gel, 1 μF, which is sandwiched between glass substrates on which source and drain electrodes were constructed.     

Amorphous-silicon-on-glass field emitter arrays

An amorphous-silicon (a-Si) field emitter array (FEA) has been fabricated on a glass substrate and characterized, At first, a 0.3-μm-thick Cr film was deposited on the glass by vacuum evaporation technique and subsequently a 1-μm-thick Si film was deposited on the Cr film by conventional RF sputtering technique with an undoped Si target at room temperature. The sputtered Si film was identified as amorphous from X-ray diffraction patterns and had a resistivity of 3-5 kΩ-cm. The FEA consists of 1-μm-high emitter tips and a gate electrode with 1.8-μm-diameter openings. This a-Si FEA with 5×5 (=25) tips exhibited a threshold voltage of 30 V and an emission current of 2 μA at a gate voltage of 100 V. Structure and emission characteristics are discussed     

Influence of substrate temperature on the performance of zinc oxide thin film transistor

Top-contact thin film transistors（TFTs） using radio frequency（RP） magnetron sputtering zinc oxide （ZnO） and silicon dioxide（SiO₂） films as the active channel layer and gate insulator layer,respectively,were fabricated.The performances of ZnO TFTs with different ZnO film deposition temperatures（room temperature, 100℃and 200℃） were investigated.Compared with the transistor with room-temperature deposited ZnO films, the mobility of the device fabricated at 200℃is improved by 94%and the threshold voltage shift is reduced from 18 to 3 V（after 1 h positive gate voltage stress）.Experimental results indicate that substrate temperature plays an important role in enhancing the field effect mobility,sharping the subthreshold swing and improving the bias stability of the devices.Atomic force microscopy was used to investigate the ZnO film properties.The reasons for the device performance improvement are discussed.     

2.6 kV 4H-SiC lateral DMOSFETs

A 4H-SiC lateral double-implanted metal-oxide-semiconductor (LDMOS) field effect transistor is fabricated in a lightly doped n-epilayer on an insulating 4H-SiC substrate. After depleting through the epilayer, the depletion region continues to move laterally toward the drain. The result is an increase in blocking voltage compared to a vertical DMOSFET fabricated in the same epilayer on a conducting substrate. A blocking voltage of 2.6 kV is obtained, nearly double the highest previously demonstrated blocking voltage for a SiC MOSFET     

Optical and electrical properties of N-doped ZnO and fabrication of thin-film transistors

Using NH3 as nitrogen source gas, N-doped ZnO (ZnO:N) thin films in c-axis orientation were deposited on glass substrates by radio frequency magnetron sputtering at room temperature. The ZnO:N thin films display significant increase of resistivity and decrease of photoluminescence intensity. As-grown ZnO:N material was used as active channel layer and Si3N4 was used as gate insulator to fabricate thin-film transistor. The fabricated devices on glasses demonstrate typical field effect transistor characteristics.     

基于介质上电润湿效应的液态场效应管

用一片ITO玻璃作为场效应管的源极,在此玻璃上分别粘贴两块相同厚度塑料薄铝片作为栅极和漏极,在两块铝片之间留下很小的平行缝隙,再分别在源极、漏极、栅极的玻璃板上涂上聚四氟乙烯(Teflon)薄膜作为亲油疏水层,采用环氧树脂作为围堰材料,这样就制备了基于电润湿效应的新型液态场效应管。通过改变栅极的电压,能够调节有色油滴的位移,从而控制源极和漏极的电流变化。完成了液态场效应管的制作,并给出了初步的测试结果。     

掺氮ZnO薄膜的光电特性及其薄膜晶体管研究

Using NH3 as nitrogen source gas, N-doped ZnO （ZnO：N） thin films in c-axis orientation were deposited on glass substrates by radio frequency magnetron sputtering at room temperature. The ZnO：N thin films display significant increase of resistivity and decrease of photoluminescence intensity. As-grown ZnO：N material was used as active channel layer and Si3N4 was used as gate insulator to fabricate thin-film transistor. The fabricated devices on glasses demonstrate typical field effect transistor characteristics.     

Low temperature polycrystalline silicon thin film transistor withsilicon nitride ion stopper

The authors have fabricated a new low temperature polycrystalline silicon (poly-Si) thin film transistor (TFT) with silicon nitride (SiN _x) ion-stopper and laser annealed poly-Si. The fabricated poly-Si TFT using SiN_x as the ion-stopper as well as the gate insulator exhibited a field effect mobility of 110 cm²/Vs, subthreshold voltage of 5.5 V, subthreshold slope of 0.48 V/dec., and on/off current ratio of ~10⁶. Low off-state leakage current of 2.4×10^-2 A/μm at the drain voltage of 5 V and the gate voltage of -5 V was achieved     

Kink-free polycrystalline silicon double-gate elevated-channelthin-film transistors

The authors report the characterization and analysis of a novel double-gate elevated-channel thin-film transistor (ECTFT) fabricated using polycrystalline silicon. The transistor has a thin channel and thick source/drain regions with a double-gate control. Using this structure, the kink effect in the I-V characteristics of a conventional TFT is completely eliminated, and leakage current at zero gate bias is reduced by over 15 times. The elimination of the kink effect and the significant reduction in leakage current are obtained due to the reduction in lateral electric field at the channel/drain junction region. Two-dimensional (2-D) device simulations are used to study the electric field reduction mechanism in the structure. Experimental results on the forward conduction and gate transfer characteristics of the structure are also presented     

Analysis of high-frequency thermal noise of enhancement mode MOS field-effect transistors

The high-frequency thermal noise in the drain and the gate of an enhancement mode MOS field-effect transistor was analyzed by using the transmission line model of the channel. The analysis gave the mean squared noise current generators of the drain and the gate and their correlation. The correlation coefficient of the drain and the gate noise was zero for zero drain voltage and was 0.395j at saturation. The noise figure of the MOS field-effect transistor was calculated from the result of the analysis. The high-frequency noise characteristics of an MOS field-effect transistor were similar to those of a junction gate field-effect transistor.     

Metal-ferroelectric-insulator-semiconductor memory FET with long retention and high endurance

A ferroelectric memory field-effect transistor (FET) with a Pt-SrBi/sub 2/Ta/sub 2/O/sub 9/-Hf-Al-O-Si gate stack was fabricated and its electrical properties were characterized. The insulating and ferroelectric layers were successively deposited by a laser ablation technique. Excellent data retention characteristics were obtained. The drain currents of on- and off-states were measured as a function of time, after /spl plusmn/6 V poling voltage applied to the gate electrode. The current ratio of the on- and off-states was more than 10/sup 6/ even after 12 days. Moreover, after 10/sup 12/ cycles of /spl plusmn/8 V pulses, this ratio was also more than 10/sup 6/.