基于Pd/SWNT/Al结构的场效应晶体管的研究

碳纳米管因具有良好的物理机械性能而得到广泛的研究,其最重要的应用之一是构建场效应晶体管(FET).文章提出并研究了一种非对称接触的单壁碳纳米管场效应晶体管(SWNT-FET),并对其电学特性进行了表征.在该器件中,SWNT被作为FET的沟道,两种不同功函数的金属被用来与SWNT形成肖特基接触;SWNT一端与低功函数金属Al形成源极,另一端与高功函数金属Pd形成漏极.该类器件可应用于下一代纳米集成电路中.     

具有石墨烯辅助导电层的碳纳米管射频场效应晶体管

采用纯度高于99%的半导体型单壁碳纳米管分散液制备碳纳米管无序网络作为射频场效应晶体管的有源沟道材料,使用单层石墨烯作为器件源漏的辅助接触电极,研制出T型栅结构的碳纳米管射频场效应晶体管。采用石墨烯加强晶体管器件的欧姆接触,降低器件的寄生电阻和寄生电容,提高器件的高频性能。实验制备的碳纳米管射频晶体管沟道长度为90nm左右,电流增益截止频率f_T达到13.5GHz,最大振荡频率f_(max)达到10.5GHz,体现了碳纳米管在射频器件应用领域的技术潜力。     

采用砷化镓场效应晶体管的18千兆赫前置放大器

引言砷化镓金属半导体场效应晶体管(MESFET)比双极晶体管噪声低,增益高,适用于高至20千兆赫左右频率下的低噪声前置放大器。金属半导体场效应晶体管的特性金属半导体场效应晶体管由高阻衬底上的薄导电层构成。N 型导电层包括源和漏两个欧姆接触以及栅的整流接触。图1示出的砷化镓金属半导体场效应晶体管中,1×200微米的栅     

美单壁碳纳米管传感器研究取得关键性进展

摩托罗拉实验室和亚利桑那州立大学日前宣布,他们在使用单壁碳纳米管场效应晶体管来感应生物和化学毒剂的研究中取得了关键进展。该研究小组发明了一种利用SWNT(单壁碳纳米管)和缩氨酸来制成低功率SWNT-FET(单壁碳纳米管场效应晶体管)的方法,SWNT-FET具有高灵敏度,并能够选择性     

WSe2场效应晶体管的源漏接触特性研究

二硒化钨(WSe2)具有双极导电特性,可以通过外界掺杂或改变源漏金属来调节载流子传输类型,是一类特殊的二维纳米材料,有望在未来集成电路中成为硅(Si)的替代材料.文章采用理论与实验相结合的方式系统分析了 WSe2场效应晶体管中的源漏接触特性对器件导电类型及载流子传输特性的影响,通过制备不同金属作为源漏接触电极的WSe2场效应晶体管,发现金属/WSe2接触的实际肖特基接触势垒高低极大地影响了晶体管的开态电流.源漏金属/WSe2接触特性不仅取决于接触前理想的费米能级差,还受到界面特性,特别是费米能级钉扎效应的影响.     

反应溅射法制备耐熔金属氮化物/GaAs肖特基结

自对准GaAs场效应晶体管工艺要求非常稳定的材料作为栅电极,经高温退火过程后它仍必须与衬底保持良好的肖特基接触。本文总结了近几年来有关耐熔金属氮化物/GaAs肖特基结的研究工作,对取得的进展及存在的问题进行了讨论。     

SiC肖特基栅JFET功率特性的研究

提出了一种新型结构的SiC结型场效应晶体管,采用肖特基接触替代P+型栅区,以降低SiC JFET的工艺复杂度,并提高器件的功率特性。建立了器件的数值模型,对不同材料和结构参数下的功率特性进行了仿真。结果表明,与PN结栅相比,肖特基栅结构可以有效降低SiC JFET的开态电阻;与常规结构的双极模式SiC JFET相比,在SiC肖特基栅JFET的栅极正偏注入载流子,同样可以有效降低器件的开态电阻,折中器件的正反向特性,但不会延长开关时间。     

1微米栅的砷化镓场效应晶体管

砷化镓肖特基势垒栅场效应晶体管,作为微波晶体管(简称GaAsSBFET)比现存的硅双极晶体管具有更低的噪声和更好的高频特性,而引人注目,现在正迅速付之实用。为了得到GaAsSBFET良好的高频特性,应使用电子迁移率大的好的晶片,实现寄生损耗小、栅长短的结构。特别是对缩短栅长做了很大的努力,现正在研究接触曝光、     

碳纳米管晶体管

随着传统的硅材料加工技术发展到极限,寻找替代硅的材料已迫在眉睫。碳纳米管因其优良的性能将成为替代硅的理想材料。本文介绍了以碳纳米管为基础的场效应晶体管的工作原理以及独特性能。与传统的金属-氧化物-半导体(MOS)场效应晶体管相比,由于碳纳米管具有单分子、准一维、高电流密度等优良特性,所以碳纳米管晶体管将很容易突破传统硅场效应晶体管的物理极限,并且在继续减小器件尺寸、解决耗能和散热问题方面具有优势。     

无结场效应管——新兴的后CMOS器件研究进展

迄今为止,现有的晶体管都是基于PN结或肖特基势垒结而构建的。在未来的几年里,CMOS制造技术的进步将导致器件的沟道长度小于10nm。在这么短的距离内,为使器件能够工作,将不得不采用非常高的掺杂浓度梯度。进入纳米领域,常规CMOS器件所面临的许多问题都与PN结相关,传统的按比例缩小将不再足以继续通过制造更小的晶体管而获得器件性能的提高。半导体工业界正在努力从器件几何形状,结构以及材料方面寻求新的解决方案。文中研究了无结场效应器件制备工艺技术及其进展,这些器件包括半导体无结场效应晶体管、量子阱场效应晶体管、碳纳米管场效应晶体管、石墨烯场效应晶体管、硅烯场效应晶体管、二维半导体材料沟道场效应晶体管和真空沟道场效应管等。这些器件有可能成为适用于10nm及以下技术节点乃至按比例缩小的终极器件。     

Single-walled carbon nanotube transistors fabricated by advanced alignment techniques utilizing CVD growth and dielectrophoresis

Single-walled carbon nanotube field effect transistors (SWNT-FETs) are fabricated by two different alignment techniques. The first technique is based on direct synthesis of an aligned SWNTs array on quartz wafer using chemical vapor deposition. The transistor with three SWNTs and atomic layer deposited (ALD) Al₂O₃ gate oxide shows a contact resistance of 280 KΩ, a maximum on-current of ?7 μA, and a high I_on/I_off ratio (>10³). The second technique is based on room temperature self-assembly of SWNT bundles using dielectrophoresis. By applying AC electric fields, we have aligned nanotube bundles between drain and source contact patterns of a transistor at room temperature. Transistors based on twisted bundle of SWNTs show high contact resistance (MΩ range) and low current drive in the order of tens of nA.     

Comparing carbon nanotube transistors - the ideal choice: a novel tunneling device design

Three different carbon nanotube (CN) field-effect transistor (CNFET) designs are compared by simulation and experiment. While a C-CNFET with a doping profile similar to a "conventional" (referred to as C-CNFET in the following) p-or n-MOSFET in principle exhibits superior device characteristics when compared with a Schottky barrier CNFET, we find that aggressively scaled C-CNFET devices suffer from "charge pile-up" in the channel. This effect which is also known to occur in floating body silicon transistors deteriorates the C-CNFET off-state substantially and ultimately limits the achievable on/off-current ratio. In order to overcome this obstacle we explore the possibility of using CNs as gate-controlled tunneling devices (T-CNFETs). The T-CNFET benefits from a steep inverse subthreshold slope and a well controlled off-state while at the same time delivering high performance on-state characteristics. According to our simulation, the T-CNFET is the ideal transistor design for an ultrathin body three-terminal device like the CNFET.     

Fabrication of Schottky barrier MOSFETs using self-assembly CoSi2 nanopatterning and spacer gate technologies

A self-assembly patterning method for generation of epitaxial CoSi₂ nanostructures was used to fabricate 50 nm channel-length MOSFETs. The transistors have either a symmetric structure with Schottky source and drain or an asymmetric structure with n⁺-source and Schottky drain. The patterning technique is based on anisotropic diffusion of Co/Si atoms in a strain field during rapid thermal oxidation. The strain field is generated along the edges of a mask consisting of 20 nm SiO₂ and 300 nm Si₃N₄. During rapid thermal oxinitridation (RTON) of the masked silicide structure, a well-defined separation of the silicide layer forms along the edge of the mask. These highly uniform gaps define the channel region of the fabricated device. The separated silicide layers act as metal source and drain. A poly-Si spacer was used as the gate contact. The asymmetric transistor was fabricated by ion implantation into the unprotected CoSi₂ layer and a subsequent out-diffusion process to form the n⁺-source. I–V characteristics of both the symmetric and asymmetric transistor structures have been investigated.     

Thin active layer a-Si:H thin-film transistors

We show that hydrogenated amorphous silicon thin-film transistors (TFT's) with active layer thickness less than 50 nm have improved performance for display applications. Using two-dimensional (2-D) modeling, we find previously observed degradation for thin active layers is due to electric field effects in the contact regions of staggered inverted devices and affects only the saturation characteristics; linear region performance actually improves with decreasing thickness. We have fabricated devices with extremely thin active layer (10 nm), and indeed find excellent linear region characteristics. In addition, direct tunneling across the undoped regions at device contacts reduces electric field effects, resulting in excellent saturation region characteristics, and gate-induced channel accumulation reduces the Schottky barrier width at direct metal contacts so that even devices without doped contact regions (i.e., tunneling contacts) are possible     

Selective Crystallization of Organic Semiconductors on Patterned Templates of Carbon Nanotubes

A method of patterning large arrays of organic single crystals is reported. Using single‐walled carbon nanotube (SWNT) bundles as patterned templates, several organic semiconductor materials were successfully patterned, including p‐type pentacene, tetracene, sexiphenylene, and sexithiophene, as well as n‐type tetracyanoquinodimethane (TCNQ). This study suggests that the selective growth of crystals onto patterned carbon nanotubes is most likely due to the coarse topography of the SWNT bundles. Moreover, we observed that the crystals nucleated from SWNT bundles and grew onto SWNT bundles in a conformal fashion. The dependence of the number of crystals on the quantity of SWNT bundles is also discussed. The crystal growth can be directly applied onto transistor source‐drain electrodes and arrays of organic single‐crystal field effect transistors are demonstrated. The results demonstrate the potential of utilizing carbon nanotubes as nucleation templates for patterning a broad range of organic materials for applications in optoelectronics.     

Low Temperature Characteristics of Schottky Barrier Single Electron and Single Hole Transistors

Schottky barrier single electron transistors (SB‐SETs) and Schottky barrier single hole transistors (SB‐SHTs) are fabricated on a 20‐nm thin silicon‐on‐insulator substrate incorporating e‐beam lithography and a conventional CMOS process technique. Erbium‐ and platinum‐silicide are used as the source and drain material for the SB‐SET and SB‐SHT, respectively. The manufactured SB‐SET and SB‐SHT show typical transistor behavior at room temperature with a high drive current of 550 μA/μm and ?376 μA/μm, respectively. At 7 K, these devices show SET and SHT characteristics. For the SB‐SHT case, the oscillation period is 0.22 V, and the estimated quantum dot size is 16.8 nm. The transconductance is 0.05 μS and 1.2 μS for the SB‐SET and SB‐SHT, respectively. In the SB‐SET and SB‐SHT, a high transconductance can be easily achieved as the silicided electrode eliminates a parasitic resistance. Moreover, the SB‐SET and SB‐SHT can be operated as a conventional field‐effect transistor (FET) and SET/SHT depending on the bias conditions, which is very promising for SET/FET hybrid applications. This work is the first report on the successful operations of SET/SHT in Schottky barrier devices.     

Asymmetric Schottky Contacts in Bilayer MoS2 Field Effect Transistors

The high‐bias electrical characteristics of back‐gated field‐effect transistors with chemical vapor deposition synthesized bilayer MoS₂ channel and Ti Schottky contacts are discussed. It is found that oxidized Ti contacts on MoS₂ form rectifying junctions with ≈0.3 to 0.5 eV Schottky barrier height. To explain the rectifying output characteristics of the transistors, a model is proposed based on two slightly asymmetric back‐to‐back Schottky barriers, where the highest current arises from image force barrier lowering at the electrically forced junction, while the reverse current is due to Schottky‐barrier‐limited injection at the grounded junction. The device achieves a photoresponsivity greater than 2.5 A W^?1 under 5 mW cm^?2 white‐LED light. By comparing two‐ and four‐probe measurements, it is demonstrated that the hysteresis and persistent photoconductivity exhibited by the transistor are peculiarities of the MoS₂ channel rather than effects of the Ti/MoS₂ interface.     

Short-channel GaAs FET fabricated like a MESFET but operating like a JFET

Normally-on GaAs field-effect transistors (FETs) having 1 ?m gate lengths and 4 ?m channel lengths were fabricated in structures grown by molecular beam epitaxy (MBE). The unique part of this device is the very thin p+/n+ structure used to replace the conventional Schottky barriers. The device fabrication procedure is identical to that of a Schottky barrier FET (MESFET), but the devices exhibit characteristics similar to that of a junction field-effect transistor (JFET). This new device, the `camel diode gate FET?, is expected to have applications in both logic and power devices.     

Fully Printed Foldable Integrated Logic Gates with Tunable Performance Using Semiconducting Carbon Nanotubes

The realization of large‐area and low‐cost flexible macroelectronics relies on both the advancements in materials science and the innovations in manufacturing techniques. In this study, extremely bendable and foldable carbon nanotube thin film transistors and integrated logic gates are fabricated on a piece of ultrathin polyimide substrate through an ink‐jet‐like printing process. The adoption of a hybrid gate dielectric layer consisting of barium titanate nanoparticles and poly(methyl methacrylate) has led to not only excellent gating effect but also superior mechanical compliance. The device characteristics show negligible amount of change after up to 1000 cycles of bending tests with curvature radii down to 1 mm, as well as very aggressive folding tests. Additionally, the electrical characteristics of each integrated logic gate can be tuned and optimized individually by using different numbers of carbon nanotube printing passes for different devices, manifesting the unique adaptability of ink‐jet printing as a digital, additive, and maskless method. This report on fully printed and foldable integrated logic gates represents an inspiring advancement toward the practical applications of carbon nanotubes for high‐performance and low‐cost ubiquitous flexible electronics.     

High performance fully-depleted tri-gate CMOS transistors

Fully-depleted (FD) tri-gate CMOS transistors with 60 nm physical gate lengths on SOI substrates have been fabricated. These devices consist of a top and two side gates on an insulating layer. The transistors show near-ideal subthreshold gradient and excellent DIBL behavior, and have drive current characteristics greater than any non-planar devices reported so far, for correctly-targeted threshold voltages. The tri-gate devices also demonstrate full depletion at silicon body dimensions approximately 1.5 - 2 times greater than either single gate SOI or non-planar double-gate SOI for similar gate lengths, indicating that these devices are easier to fabricate using the conventional fabrication tools. Comparing tri-gate transistors to conventional bulk CMOS device at the same technology node, these non-planar devices are found to be competitive with similarly-sized bulk CMOS transistors. Furthermore, three-dimensional (3-D) simulations of tri-gate transistors with transistor gate lengths down to 30 nm show that the 30 nm tri-gate device remains fully depleted, with near-ideal subthreshold swing and excellent short channel characteristics, suggesting that the tri-gate transistor could pose a viable alternative to bulk transistors in the near future.