Fabrication and characterization of lateral field-emitter triodes

The author fabricated a field-emitter triode with tungsten electrodes arranged laterally on a quartz glass substrate by using the photolithography and dry etching techniques. The device consists of an array of 170 field-emitter tips with a 10-μm pitch, a columnar gate, and an anode. The emission characteristics followed the Fowler-Nordheim tunneling theory. The mutual conductance was about 0.02 μS at an anode voltage of 300 V. The authors improved the fabrication process to obtain an emitter with an operating voltage of about 100 V     

Enhancement of electron emission efficiency and stability ofmolybdenum-tip field emitter array by diamond like carbon coating

The effect of diamond like carbon (DLC) films, coated by a layer-by-layer technique using PECVD (plasma enhanced chemical vapor deposition) on the electron emission characteristics of molybdenum (Mo)-tip field emitter array (FEA) is examined. The turn-on voltage was lowered from 80 V for the Mo-tip to 65 V for the DLC-coated Mo-tip FEA while the maximum emission current was increased from 140 μA for the Mo-tip to 320 μA for the DLC-coated Mo-tip FEA composed of 900 emitters. For an anode current of 0.1 (μA/emitter) the gate voltage for the DLC-coated Mo-tip FEA and Mo-tip FEA was about 87 and 107 V, respectively. It was also confirmed that the emission current of a DLC-coated Mo-tip FEA was more stable than that of a Mo-tip FEA     

Highly uniform and low turn-on voltage Si field emitter arraysfabricated using chemical mechanical polishing

Turn-on voltage of about 30 V is observed in 1-μm gate-aperture Si field emitter arrays fabricated using oxidation sharpening and chemical mechanical polishing. Small emitter tip radius (~10 nm) was achieved from low temperature oxidation sharpening. The gate leakage current is observed to be less than 0.01% of emitter current over the range of measurement. Devices show excellent emission uniformity for different sized arrays. Current saturation was observed at high gate voltages because of low dopant concentration of the substrate. Below the saturation region, the current-voltage characteristics obey the Fowler-Nordheim field emission theory     

Effect of diamond-like carbon coating on the emissioncharacteristics of molybdenum field emitter arrays

We have studied the electron emission characteristics of Mo field emitter arrays (FEAs) using a diamond-like carbon (DLC) film deposited by a layer-by-layer technique using plasma enhanced chemical vapor deposition. The turn-on voltage was lowered from 55 to 30 V by a 20 nm thick hydrogen-free DLC coating and maximum emission current was increased from 166 to 831 μA. Also the gate voltage required to get the anode current of 0.1 (μA/emitter) decreases from 77 to 48 V. Furthermore, the emission current from DLC coated Mo FEAs is more stable than that of noncoated Mo FEAs     

Demonstration of low voltage field emission

The authors describe field emission from a thin-film field emitter array. The process used to fabricate the field emitters is based on the mold technique described by H.F. Gray and R.F. Greene (US patent 4,307,507). Each emitter chip consists of a 10×10 square array of field emitter tips and associated lead bonding pads. There is a 10-μm spacing between emitter tips. The bare chips were packaged by mounting to an alumina substrate, four to eight chips per substrate. The chips were tested in a demountable vacuum system equipped with a movable anode. The testing apparatus makes it possible to accurately measure currents as low as 100 nA at low duty. Fowler-Nordhein-like current-voltage characteristics were measured for most of the chips tested, indicating field emission. Substantial emission currents were observed at less than 20 V. The emitted current was collected almost entirely at the anode: the measured gate current was 1 to 5% of the emitted current     

High current density Si field emission devices with plasmapassivation and HfC coating

A novel self-aligned process was developed to fabricate gated Si field emission devices. At a gate voltage of 100 V, the emission current from an array of 100 tips increased from 283 to 460 μA and the turn-on voltage decreased from 31 to 21 V after H₂ plasma passivation using an inductively coupled plasma (ICP) source for 2 min. The improvements correspond to a 1.28-eV reduction in the effective work function of the emitters and the instability of the emission current decreased from ±1,25 to ±0.25% after H₂ plasma passivation. Emitter tips were also coated with Mo silicide and HfC. The emission current increased from 230 μA for uncoated emitters to 268 μA for emitters coated with Mo silicide and 389 μA for emitters coated with HfC. The turn-on voltage decreased from 50 to 41 and 25 V while the breakdown voltage increased from 126 to 129 and 143 V when Mo silicide and HfC were used for coating, respectively, which correspond to reductions of 0.95 and 2.23 eV, respectively, in the effective work function of the emitters. Single emitter tips have similar emission characteristics as high-density field emitter arrays, indicating excellent emission uniformity from the arrays     

A novel approach for focusing electron beams using low-cost ceramicgrid [field emitter arrays]

A low-cost ceramic grid was used as a stand-alone focusing electrode in field emitter arrays to obtain high brightness and small electron beam size. The ceramic grid with an array of 200-μm holes was made from DuPont 591 with low-cost equipment. Beam size is controllable by the voltage applied to the focusing grid. Light intensity profiles were measured and analyzed. The full width at half maximum (FWHM) of the light profile excited by electron emission from 30-μm wide field emitter arrays is 60 μm at 5000 V with 6 mm anode-cathode separation. At an anode voltage of 2000 V and gate voltage of 55 V, focusing is optimized at a focusing voltage of 30 V. Arc-free operation at 10 kV was achieved, thereby promoting improved phosphor efficiency. This focusing approach may lead to improve lifetimes for field emission displays and other vacuum microelectronic devices by significantly increasing the total vacuum volume and providing a means for improved getter utilization     

Active‐Matrix Field Emission Display with Amorphous Silicon Thin‐Film Transistors and Mo‐Tip Field Emitter Arrays

We present, for the first time, a prototype active‐matrix field emission display (AMFED) in which an amorphous silicon thin‐film transistor (a‐Si TFT) and a molybdenum‐tip field emitter array (Mo‐tip FEA) were monolithically integrated on a glass substrate for a novel active‐matrix cathode (AMC) plate. The fabricated AMFED showed good display images with a low‐voltage scan and data signals irrespective of a high voltage for field emissions. We introduced a light shield layer of metal into our AMC to reduce the photo leakage and back channel currents of the a‐Si TFT. We designed the light shield to act as a focusing grid to focus emitted electron beams from the AMC onto the corresponding anode pixel. The thin film depositions in the a‐Si TFTs were performed at a high temperature of above 360°C to guarantee the vacuum packaging of the AMC and anode plates. We also developed a novel wet etching process for n⁺‐doped a‐Si etching with high etch selectivity to intrinsic a‐Si and used it in the fabrication of an inverted stagger TFT with a very thin active layer. The developed a‐Si TFTs performed well enough to be used as control devices for AMCs. The gate bias of the a‐Si TFTs well controlled the field emission currents of the AMC plates. The AMFED with these AMC plates showed low‐voltage matrix addressing, good stability and reliability of field emission, and good light emissions from the anode plate with phosphors.     

Surface morphology and I-V characteristics of single-crystal,polycrystalline, and amorphous silicon FEA's

This letter reports the surface morphology and current-voltage (I-V) characteristics of single-crystal silicon (c-Si), polycrystalline silicon (poly-Si), and amorphous silicon (a-Si) field emitter arrays (FEAs). As-deposited a-Si film has a smoother surface than poly-Si film. The surface morphology of the a-Si remains smooth even after phosphorus doping and oxidation at 950°C to be improved in emission characteristics, i.e., smaller anode current deviation among arrays smaller gate current, and higher failure voltage than those of poly-Si FEAs. Such improved characteristics can be explained by the smooth surface morphology which is kept during doping and oxidation. The surface roughness and emission characteristics of a-Si FEAs are comparable to those of c-Si FEAs     

High-speed polysilicon emitter—base bipolar transistor

High-speed polysilicon emitter and base electrode Si n-p-n bipolar devices were fabricated showing performances of 55-ps ECL gate delay (FI = FO = 1) and cutoff frequency of 15.6 GHz (at VCE= 3 V, LVCEO= 6.8 V). These devices were built on an oxide-isolated substrate produced by planarizing oxide which is deposited after device Si island etching. The final emitter width is 0.5 µm, and a 1.3-µm-thick arsenic-doped LPCVD epitaxial layer of 0.25 Ω.cm is utilized. Emitter-base (E-B) junctions formed by direct implantations of arsenic and boron ions into a substrate were compared with junctions induced by diffusing dopants from implanted polysilicon. In the case of diffused junctions, an emitter junction depth of less than 500 Å along with a 1000-Å base width can be obtained.     

Field emission characteristics of CoSi2/TaN-coatedsilicon emitter tips

This work has improved the emission characteristics of Si emitter tips by coating a CoSi₂/TaN bilayer on the tips. The CoSi₂ layer was grown in situ by a reactive chemical-vapor deposition of cyclopentadienyl dicarbonyl cobalt at 650°C. The TaN was then deposited on the CoSi₂ layer at 550°C by a reactive sputtering of Ta with N as a reactive gas. The CoSi₂/TaN-coated emitters showed a lower turn-on voltage and higher emission current than the CoSi₂- or TaN-coated emitters due to the low work function by TaN and the easy transport of electron by CoSi₂ with low resistivity. The long-term emission stability of CoSi₂/TaN-coated Si emitter was as good as TaN-coated emitter     

Silicide application on gated single-crystal, polycrystalline andamorphous silicon FEAs. I. Mo silicide

In order to improve both the level and the stability of electron field emission, the tip surface of silicon field emitters have been coated with a molybdenum layer of thickness 25 nm through the gate opening and annealed rapidly at 1000°C in inert gas ambient. The gate voltages of single-crystal silicon (c-Si), polycrystalline silicon (poly-Si) and amorphous silicon (a-Si) field emitter arrays (FEAs) required to obtain anode current of 10 nA per tip are 90 V, 69 V, and 84 V, respectively. In the case of the silicide emitters based on c-Si, poly-Si and a-Si, these gate voltages are 76 V, 63 V, and 69 V, respectively. Compared with c-Si, poly Si and a-Si field emitters, the application of Mo silicide on the same silicon field emitters exhibited 9.6 times, 2.1 times, and 4.2 times higher maximum emission current, and 6.1 times, 3.7 times, and 3.1 times lower current fluctuation, respectively. Moreover, the emission currents of the silicide FEAs depending on vacuum level are almost same in the range of 10^-9~10^-6 torr. This result shows that silicide is robust in terms of anode current degradation due to the absorption of air molecules     

Process and device performance of a high-speed double poly-Sibipolar technology using borosenic-poly process with coupling-baseimplant

Use of boron and arsenic diffusions through an emitter polysilicon film (borosenic-poly emitter-base process) produces a transistor base width of less than 100nm with an emitter junction depth of 50 nm and an emitter-to-base reverse leakage current of approximately 70 pA. The borosenic-poly process resolves both the channeling and shadowing effects of a sidewall-oxided spacer during the base boron implantation. The process also minimizes crystal defects generated during the emitter and base implantations. The coupling-base boron implant significantly improves a wide variation in the emitter-to-collector periphery punchthrough voltage without degrading the emitter-to-base breakdown voltage current gain, cutoff frequency, or ECL gate delay time. A deep trench isolation with 4-μm depth and 1.2-μm width reduces the collector-to-substrate capacitance to 9 fF, while maintaining a transistor-to-transistor isolation voltage of greater than 25 V. The application of self-aligned titanium silicide technology to form polysilicon resistors without holes and to reduce the sheet resistance of the emitter and collector polysilicon electrodes to 1 Ω/square is discussed     

Feasibility of an Ag-alloy film as a thin-film transistor liquid-crystal display source/drain material

The Ag-alloy films have been investigated as source/drain materials applicable to thin-film transistor liquid-crystal displays (TFT-LCDs). The Ag-alloy consisting of 0.9at.%Pd, 1.7at.%Cu (designated APC) showed a resistivity that was lower than one-half that of AlNd. It also had good contact characteristics with amorphous Si (a-Si). In addition, the Ag/Si was stable after heating to above 700°C, requiring no diffusion barrier to prevent reaction between Ag and Si. Pure Ag films deposited on glass by DC magnetron sputtering showed severe hillock formation, hole growth, and agglomeration upon annealing in air. In comparison, the APC-alloy film exhibited improved resistance to agglomeration. Further, inverted-staggered back-channel-etch hydrogenated amorphous silicon (a-Si:H) TFTs using an APC-alloy film as a source/drain material had a threshold voltage of 4 V. A structure of single layers of gate-APC alloys and source/drain-APC alloys leads to lower costs and productivity improvements of large-area, high-resolution, active-matrix LCDs, such as 40-in. size panels through process simplification.     

Ultra sharp crystalline silicon tip array used as field emitter

This article describes the fabrication of single crystal silicon field emission tip arrays. Each array consists of 2500 tips. We used 4 in. (100) oriented n type silicon wafers 0.008 – 0.020 Ωcm, Sb doped. The tips were formed using a RIE process. We achieved crystalline emitter tip radiuses of 1.5 – 2 nm. The extraction grid is a self aligned, sputter deposited Ti_0.1W_0.9 film. The radiuses of the extraction grid apertures range from 300 to 150 nm and have a tip to tip spacing from 10 to 5 μm. The testing was done in vacuum with a distance of 500 μm between extraction grid and anode. We have seen maximum stable array currents up to 2 μA. An anode current of 10 nA was initially detected at a minimal gate bias of about 14 V.     

Bottom-gate poly-Si thin film transistors using XeCl excimer laserannealing and ion doping techniques

High mobility bottom-gate poly-Si thin film transistors (TFTs) have been successfully fabricated on a hard glass substrate using XeCl excimer laser annealing and ion doping techniques. The authors used an a-Si:H film which is deposited by a plasma-enhanced chemical vapor deposition (PECVD) as a precursor film, and then they crystallized the a-Si film by XeCl excimer laser annealing. The maximum field effect mobility and grain size obtained were 200 cm²/V-s (n-channel), and 250 nm, respectively. The poly-Si TFTs showed excellent transfer characteristics, and an ON/OFF current ratio of over 10⁶ was obtained. Successful control of the threshold voltage within 4 V using an ion doping technique is also demonstrated     

电泳法制备平栅极碳纳米管场发射阴极及场发射特性研究

采用电泳法在ITO玻璃基板上选择性制备了碳纳米管(CNTs)阴极薄膜,采用电子扫描(SEM)分析了CNTs薄膜的表面形貌,并测试了碳纳米管阴极的场致发射特性.结果表明,利用电泳法制得的碳纳米管阴极薄膜均匀性、致密性良好,且具有较大发射电流密度;通过控制共面栅控CNTs场发射阴极的栅极电位能够有效控制阴极的场发射电流密度...     

Ga2O3(Gd2O3)/InGaAsenhancement-mode n-channel MOSFETs

We have demonstrated the first Ga₂O₃(Gd₂O₃) insulated gate n-channel enhancement-mode In_0.53Ga_0.47As MOSFET's on InP semi-insulating substrate. Ga₂O₃(Gd₂ O₃) was electron beam deposited from a high purity single crystal Ga₅Gd₃O₁₂ source. The source and drain regions of the device were selectively implanted with Si to produce low resistance ohmic contacts. A 0.75-μm gate length device exhibits an extrinsic transconductance of 190 mS/mm, which is an order of magnitude improvement over previously reported enhancement-mode InGaAs MISFETs. The current gain cutoff frequency, f_t, and the maximum frequency of oscillation, f_max, of 7 and 10 GHz were obtained, respectively, for a 0.75×100 μm² gate dimension device at a gate voltage of 3 V and drain voltage of 2 V     

The amorphous Si/SiC heterojunction color-sensitive phototransistor

An amorphous Si/SiC heterojunction color-sensitive phototransistor was successfully fabricated by plasma-enhanced chemical vapor deposition. The structure is glass/ITO/a-Si(n⁺-i)/a-SiC(p⁺-i-n⁺)/Al. The device is a bulk barrier transistor with wide-bandgap amorphous SiC emitter and base. The phototransistor revealed a very high optical gain of 40 and a response speed of 10 µs at an input light power of 5 µW and a collector current of 0.12 mA at a voltage of 14 V. The peak response occurs at 610 nm under 1-V bias and changes to 420 and 540 nm under 7- and 13-V biases, respectively.     

Hydrogenated amorphous silicon thin-film transistor with a thingate insulator

Thinning the gate insulator in an hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) has been studied in a coplanar structure. The threshold voltage decreases with decreasing gate insulator thickness without changing the field effect mobility significantly. The reduction in the threshold voltage is due to the decrease in the charge traps in the SiN_x and in its film thickness. The coplanar a-Si:H TFT with a gate insulator thickness of 35 nm exhibited a field effect mobility of 0.45 cm²/Vs and a threshold voltage of 1.5 V. The thickness of the gate insulator can be decreased in the coplanar a-Si:H TFTs because of the planarized gate insulator