具有冗余设计的铜互连线电迁移可靠性评估

铜互连的电迁移可靠性与晶粒结构、几何结构、制造工艺以及介质材料等因素有着密切的关系。分别试制了末端有一定延伸的互连线冗余结构设计的样品,以及无冗余结构的互连线样品,并对样品进行了失效加速测试。测试结果显示,采用冗余结构设计的互连线失效时间更长,具有更好的抗电迁移可靠性。对冗余结构的失效模式进行了讨论,并结合互连线的制造工艺,指出采用冗余结构设计的互连线可以在有效改善互连线的电迁移特性,而且不会引入其他影响可靠性的因素,是一种有效提高铜互连电迁移可靠性的方法。     

0.13μm铜互连工艺鼓包状缺陷问题的解决

传统集成电路制造工艺主要采用铝作为金属互连材料,但是随着晶体管尺寸越来越小,在0.13μm及以上制程中,一般采用铜大马士革互连工艺来提高器件的可靠性。铜互连工艺中需要用氮化硅作为穿孔图形蚀刻的阻挡层,由于氮化硅材质具有很强的应力,再加上制程中的热反应和蚀刻效应就会造成氮化硅层从界面掀起从而形成一种鼓包状缺陷(bubble defect)。文章通过调整并控制铜金属连线层间氧化电介质层的蚀刻速率,改变有机介质层(BARC)的沉积方法,以及改进产品的电路设计的检验规则,从而解决鼓包状缺陷的产生,降低产品芯片的报废率,提高产品的良率。     

铜互连新型阻挡层材料的研究进展

铜互连阻挡层材料起到防止铜与介质材料发生扩散的重要作用。因此,阻挡层材料需要满足高稳定性、与铜和介质材料良好的粘附性以及较低的电阻。自1990年代以来,氮化钽/钽(TaN/Ta)作为铜的阻挡层和衬垫层得到了广泛的应用。然而,随着晶体管尺寸微缩,互连延时对芯片速度的影响越来越重要。由于TaN/Ta的电阻率高且无法直接电镀铜,已经逐渐难以满足需求。文章综述了铜互连阻挡层材料的最新进展,包括铂族金属基材料、自组装单分子层、二维材料和高熵合金,以期对金属互连技术的发展提供帮助。     

Cu互连应力迁移失效有限元分析

为研究铜互连系统中各因素对残余应力及应力迁移失效的影响,建立了三维有限元模型,用ANSYs软件分析计算了Cu互连系统中的残余应力分布情况,并对比分析了不同结构、位置及层间介质材料的互连系统中的残余应力及应力梯度.残余应力在金属线中通孔正下方M2互连顶端最小,在通孔内部达到极大值,应力梯度在Cu M2互连顶端通孔拐角底部位置达到极大值.双通孔结构相对单通孔结构应力分布更为均匀,应力梯度更小.结果表明,空洞最易形成位置由应力和应力梯度的大小共同决定,应力极大值随通孔直径和层间介质介电常数的减小而下降,随线宽和重叠区面积的减小而上升.应力梯度随通孔直径、层间介质介电常数和重叠区面积的减小而下降,随线宽减小而上升.     

步入深亚微米的互连技术《半导体国际》互连技术在线研讨会

半导体产业发展至今,大部分时间内AI互连技术都扮演了极为重要的角色,铝材料和SiO2一直作为制造集成电路中的微连线或配线;0．13微米以下的设计标准中,采用铝微连线制造的器件开始在可靠性方面出现问题．铜互连工艺应运而生。基于双大马士革的Cu工艺、高／低K介质材料等已成为业界热门话题,进一步改善互连性能的需求,推动今后互连技术的发展。集成电路技术的进一步发展对互连性能提出更高的要求。     

《半导体国际》互连技术研讨会2008

主题步入深亚微米的互连技术半导体产业发展至今,大部分时间内Al互连技术都扮演了极为重要的角色,铝材料和SiO2一直作为制造集成电路中的微连线或配线：0.13微米以下的设计标准中,采用铝微连线制造的器件开始在可靠性方面出现问题,铜互连工艺应运而生。基于双大马士革的Cu工艺,高／低K介质材料等已成为业界热门话题,进一步改善互连性能的需求,推动今后互连技术的发展。     

铜互连可靠性分析

在简要的对铜互连和铝互连进行了比较后,本文从材料特性和集成工艺两方面讨论了铜互连和铝互连对可靠性的不同影响,并详细的分析了一个关键的可靠性失效机理:电迁移(包括通孔损耗和连线损耗).最后讨论了影响铜电迁移的一些工艺要素,如通孔、阻挡层和覆盖层.     

Cu互连线显微结构和应力的AFM及SNAM分析

在ULSI中采用Cu互连线代替Al以增加电子器件的传输速度和提高器件的可靠性，Cu的激活能约为1．2eV，而Al的激活能约为0．7eV,Cu互连线寿命约为Al的3－5倍。Cu大马士革互连线的制备工艺为：在硅衬底上热氧化生成的SiO2上开出凹槽，在凹槽中先后沉积阻挡层Ta和晶种层Cu，然后由电镀的Cu层将凹槽填满，最后采用化学机械抛光将凹槽外多余的Cu研磨掉，Cu互连线的尺寸为：200um长，0．5μm厚，宽度分别为0．35，0．5，1至3μm不等，部分样品分别在200℃，300℃和450℃下经过30min退火。利用原子力显微镜（AFM）和扫描近场声学显微镜（SNAM），同时获得形貌像和声像，分别了Cu大马士革凹槽构造引起的机械应力和沉积引起的热应力对Cu互连线显微结构及可靠性的影响，SNAM是在Topometrix公司AFM基础上建造的实验装置，实验采用的机械振动频率在600Hz-100kHz之间。分析测试结果如下：1．AFM和SNAM可以实现对微米和亚微米特征尺寸的Cu互连线的局域应力分布和显微结构的原位分析。2．采用AFM，TEM、XRD观察和测试了Cu互连线的晶体结构，分析了大马士革凹槽工艺 对Cu晶粒尺寸及取向的影响。平坦的沉积态Cu膜的晶粒尺寸约为100nm；而由大马士革工艺制备的凹槽中的Cu互连线的晶粒尺寸约为70－80nm，凹槽结构抑制了晶粒生长，平坦的沉积态Cu膜有较强的（111）织构；而凹槽中的Cu互连线的（111）织构减弱，（200）和其它的晶体取向分量增强。3．SNAM声阻尼信号对材料局域应力的变化敏感，SNAM声图衬底可显示出局域应力的分布，在沉积态的Cu互连线声图中，金属和SiO2介电层的界面处像衬度强，表明该处为应力较高的区域，而在退火后的Cu互连线的声图中，金属和SiO2介电层的界面处像衬度弱，表明退火后该处应力减小，我们对Cu膜进行了宏观应力的测试，退火后应力值从沉积态的661MPa减少至359Mpa，这与SNAM声成像的结果相符合。     

双大马士革工艺的发展及挑战

随着CMOS晶体管尺寸不断缩小到次微米级,正如摩尔定律的预测,在高效率、高密度集成电路中的晶体管数量上升到几千万个。这些数量庞大的有源元件的信号集成需要多达八层的高密度金属连线,然而这些金属互连线带来的电阻和寄生电容已经成为限制这种高效集成电路速度的主要因素。基于这个因素的推动,半导体工业从原来的金属铝互连线工艺发展成金属铜互连线,同时低k值材料替代了二氧化硅成为金属层间的绝缘介质。金属铜减少了金属连线层间的电阻,同时增强了电路稳定性;低k值介质则减少了金属连线层之间的寄生电容。     

45nm双大马士革Cu互连逆流电迁移双峰现象及改善

集成电路中金属连线的逆流电迁移(EM)的双峰失效现象在45 nm双大马士革低k材料铜布线工艺中变得尤为突出,介绍了由于空洞存在于连接电路导致电迁移的早期失效,总结出两个早期失效的主要原理:分别是空洞形成在通孔以及浅槽与通孔的斜面,这是由于淀积扩散阻挡层和铜工艺在上述两个地方存在弱点,越薄的扩散阻挡层厚度对EM越不利。因为偏薄的扩散阻挡层不利于阻挡铜扩散,尤其在通孔的侧壁和边角斜面,这样在测试电迁移的高温大电流下,铜在通孔侧壁和边角斜面处易扩散而形成空洞,最终导致芯片失效。实验表明可以通过优化双大马士革结构通孔以及浅槽与通孔的斜面的长宽比(AR)减少消除这些弱点。介质层(ILD)的厚度,浅槽的深度以及通孔的关键尺寸可以作为调节AR的主要方法。     

Finite element simulation of hydrostatic stress in copper interconnects

This work focuses on numerical modeling of hydrostatic stress,which is critical to the formation of stress-induced voiding(SIV) in copper damascene interconnects.Using three-dimensional finite element analysis, the distribution of hydrostatic stress is examined in copper interconnects and models are based on the samples, which are fabricated in industry.In addition,hydrostatic stress is studied through the influences of different low-k dielectrics,barrier layers and line widths of copper lines,and the results indicate that hydrostatic stress is strongly dependent on these factors.Hydrostatic stress is highly non-uniform throughout the copper structure and the highest tensile hydrostatic stress exists on the top interface of all the copper lines.     

互连宽度对铜互连应力可靠性的影响

基于Cu的随动强化模型,用二维有限元分析方法,模拟分析了不同互连宽度对Cu互连热应力分布的影响。研究发现,当互连尺寸减小到一定宽度后,静水应力先减小,后略有增加;随线宽的减小,等效塑性应变的最大值逐渐减小,塑性应变最大值的位置由Cu互连上界面处转向Cu互连上界面边角处,而发生等效塑性应变的区域先减小后增加。讨论了在不同Cu互连结构条件下,应力状态和塑性应变对Cu互连可靠性的影响。     

Stress analysis of 3-dimensional IC package as function of structural design parameters

Solid Liquid Inter-Diffusion (SLID) is a technology that has recently been utilized to fabricate 3D ICs. Since application of this technology is in its infancy stages, manufacturability and reliability of these bonds are still under heavy investigations. This study presents an elastic-plastic finite element and analytical analyses that were implemented to evaluate effect of package design parameters on thermo-mechanical reliability of the SLID bonds and copper interconnects. A numerical experiment is designed in which several design parameters; die thickness, bond size, underfill stiffness and substrate thickness, are varied in 3 levels. Stress in SLID bonds and in copper interconnects were evaluated using the 3-dimensional finite element analysis as well as an analytical approach. The results show that die and substrate thicknesses are the most influential factors among the selected parameters on stress at the interface and on copper interconnects. Main effect results for stress analysis in SLID bonds using finite element shows that die thickness and underfill stiffness are the most influential factors in defining stress at SLID bonds. Results of the analytical approach confirm the finite element analysis. It is shown that effect of interconnect size and pitch is very small compared to die thickness. In average increasing die thickness increases both shear and peeling stresses at the interfaces and copper interconnects.     

45 nm芯片铜互连结构低k介质层热应力分析

采用铜互连工艺的先进芯片在封装过程中,铜互连结构中比较脆弱的低介电常数(k)介质层,容易因受到较高的热机械应力而发生失效破坏,出现芯片封装交互作用(CPI)影响问题.采用有限元子模型的方法,整体模型中引入等效层简化微小结构,对45 nm工艺芯片进行三维热应力分析.用该方法研究了芯片在倒装回流焊过程中,聚酰亚胺(PI)开口、铜柱直径、焊料高度和Ni层厚度对芯片Cu/低κ互连结构低κ介质层应力的影响.分析结果显示,互连结构中间层中低κ介质受到的应力较大,易出现失效,与报道的实验结果一致;上述四个因素对芯片低κ介质中应力影响程度的排序为:焊料高度＞PI开口＞铜柱直径＞Ni层厚度.     

Reliability challenges for copper interconnects

In the past few years, copper has been widely used as interconnect metallization for advanced ultralarge-scale integration (ULSI) circuits. Due to the unique chemical properties of copper compared to its predecessor, aluminum, different integration processes must be used for circuit fabrication, that is, the damascene versus reactive ion etch (RIE) process. This difference in integration processes introduces a series of reliability concerns for copper interconnects. After a brief comparison of copper and aluminum interconnects, this article discusses the impact of the differences in the material properties and integration process on reliability. Details are provided on two advanced metallization reliability failure mechanisms: electromigration and stress migration. For copper interconnects, the interface between the cap and the copper metal serves as the fast diffusion path. To improve copper interconnect reliability, development efforts have focused on suppressing copper or copper vacancy diffusion along the interface. Two copper interfaces, the copper/cap interface and the copper/liner (or diffusion barrier) interface, are critical for copper reliability. For commonly used liners, such as Ta/TaN, the copper/liner interface is relatively easy to control compared to the copper/cap interface. For dual-damascene copper lines, a copper via is used to connect the lower level to the upper level. Unlike the robust tungsten stud used in aluminum interconnects, the copper via has been identified as a weak link in dual-damascene copper connections; the majority of early reliability failures can be attributed to the copper vias. The three most critical process factors and elements affecting copper interconnect reliability are copper vias and interfaces and the liner coverage. Using a low-k dielectric with a copper interconnect introduces several new challenges to reliability, including dielectric breakdown, temperature cycle, and stability within packages. Extensive knowledge is urgently needed to understand these issues.     

Thermomechanical response and stress analysis of copper interconnects

This study is devoted to thermomechanical response and modeling of copper thin films and interconnects. The constitutive behavior of encapsulated copper film is first studied by fitting the experimentally measured stress-temperature curves during thermal cycling. Significant strain hardening is found to exist. Within the continuum plasticity framework, the measured stress-temperature response can only be described with a kinematic hardening model. The constitutive model is subsequently used for numerical thermomechanical modeling of Cu interconnect structures using the finite element method. The numerical analysis uses the generalized plane strain model for simulating long metal lines embedded within the dielectric above a silicon substrate. Various combinations of oxide and polymer-based low-k dielectric schemes, with and without thin barrier layers surrounding the Cu line, are considered. Attention is devoted to the thermal stress and strain fields and their dependency on material properties, geometry, and modeling details. Salient features are compared with those in traditional aluminum interconnects. Practical implications in the reliability issues for modern copper/low-k dielectric interconnect systems are discussed.     

制备Cu互连悬空结构的新型工艺研究

为了降低集成电路中的互连延迟,采取了一种新型的集成电路Cu互连工艺,以掩膜电镀的方法制备Cu互连的叠层结构,借鉴MEMS工艺的牺牲层技术,用浓磷酸对Al2O3牺牲层进行湿法刻蚀,不仅在互连金属间介质层而且在层内介质层都形成了以空气为介质的Cu互连悬空结构.用一种叉指测试结构对以空气和聚酰亚胺为介质的互连性能进行了比较,结果表明,采用空气介质减小了互连线耦合电容,为进一步降低集成电路的互连延迟提供了途径.     

Microsampling technique for EBSP inspection on the cross-sections of copper trench lines in ULSIs

The crystal microstructure of copper interconnects in ultra large scale integrations (ULSIs), depends on factors such as the trench line width and patterns. Therefore, inner crystal characterisation of the desired trench lines composed of copper is required. Electron backscatter diffraction pattern (EBSP) inspection has become a powerful technique for analysing the crystal characterisation of interconnects. However, EBSP inspection is sensitive to surface conditions such as contamination and strain. In this study, we applied the focused ion beam (FIB) technology, particularly, the microsampling technique to the preparation of samples for EBSP inspection on the cross-sections of the copper trench lines. As a result, we demonstrate that a damaged layer composed of a crystalline substance is formed on the plane of the copper as revealed by the 30 kV Ga(+) FIB milling, but an EBSP signal is detectable. In conclusion, the cross-sectional sample preparation technique employing microsampling is found to be very powerful for analysing the inner crystal characteristics of the desired copper trench lines by EBSP inspection.     

Impact of process steps on electrical and electromigration performances of copper interconnects in damascene architecture

The impact of IC fabrication process steps on electrical and reliability characteristics of dual damascene copper interconnects has been analyzed. It is demonstrated that thermal treatments could have a negative impact on electrical performances unless a suitable encapsulation step of copper lines is performed. Electromigration performances are also strongly affected by annealing and the role that impurities have in dominating the diffusion paths is evidenced by experiments on differently fabricated copper structures of various widths.     

Characterization of copper grain growth limitations inside narrow wires depending of overburden thickness

With the downscaling of feature dimensions, copper interconnects exhibit properties differing from bulk or film material. Resistivity increases and limits electrical performances, and reliability of interconnects becomes a more important challenge for each new technological node. In this study, we present an approach of copper grain growth control inside narrow wires by adding a step between the copper electro-chemical deposition (ECD) and the chemical-mechanical polishing (CMP). This step corresponds to a partial CMP step (pre-CMP) and is applied after ECD and before anneal in order to modify the copper overburden thickness. Depending on the targeted thickness, copper grain growth occurs during anneal with different efficiencies. Crystallization and grain growth behaviour inside wires is investigated with focused ions beam (FIB). We present here our methodology for sample preparation and characterization. Results are focused on electrical variations and on morphological aspects of copper crystallization and grain growth inside lines observed with various overburden thicknesses.