n—CdTe Schottky势垒薄膜太阳能电池中嵌入p型层对其势垒高度影响的计算机

通过求解Ｐｏｉｓｓｏｎ方程，对热平衡态金属：ｐ－ｎＣｄＴｅＳｃｈｏｔｔｋｙ势垒薄膜太阳能电池进行计算机数值模拟，嵌入的ｐ型层增大传统金属，ｎ－ＣｄＴｅ结有效Ｓｃｈｏｔｔｋｙ势垒高度与ｐ型层厚度，掺杂浓度以及ｎ－ＣｄＴｅ本底电阻率有依赖关系，最后讨论嵌入ｐ型层增加ＣｄＴｅＳｃｈｏｔｔｋｙ势叠太阳电池对光生载流子的收集作用。     

CdTe p—i—n薄膜太阳能电池热平衡态数值分析

通过应用Ｓｃｈａｒｆｅｔｔｅｒ－Ｇｕｍｍｅｌ解法数值求解Ｐｏｉｓｓｏｎ方程，对热平衡态ｐ（ＺｎＴｅ）／ｉ（ＣｄＴｅ）／ｎ（ＣｄＳ）薄膜太阳能电池进行计算机数值模拟。结果表明，ｐ（ＺｎＴｅ）／ｉ（ＣｄＴｅ）／ｎ（ＣｄＳ）的能带结构有利于光生载流子传输与收集，ＣｄＴｅ中高内建场提高了光生载流子通过有源区的输运能力，对ＣｄＴｅ进行适量Ｐ型掺杂还能提高其电池的短波收集效率。     

HgTe／CdTe超晶格的分子束外延生长和电容—电压谱研究

在ｐ－型ＨｇＴｅ／ＣｄＴｅ超晶格材料上制作金属－绝缘体－半导体（ＭＩＳ）结构。报道了ＨｇＴｅ／ＣｄＴｅ超晶格的分子束外延生长、器件制作和测量结果。研究表明，比较宽的ＣｄＴｅ势垒阻碍了少子（电子）到界面的迁移，在７７Ｋ强反型区域的低频电容不能达到绝缘层电容，类似于普遍ＭＩＳ器件的高频Ｃ－Ｖ曲线。     

HgTe／CdTe超晶格的分子束外延生长和电容－电压谱研究

在ｐ－型ＨｇＴｅ／ＣｄＴｅ超晶格材料上制作金属－绝缘体－半导体（ＭＩＳ）结构．报道了ＨｇＴｅ／ＣｄＴｅ超晶格的分子束外延生长、器件制作和测量结果．研究表明，比较宽的ＣｄＴｅ势垒阻碍了少子（电子）到界面的迁移，在７７Ｋ强反型区域的低频电容不能达到绝缘层电容，类似于普通ＭＩＳ器件的高频Ｃ—Ｖ曲线．     

CdTe-HgCdTe界面的电导机制

本文研究了ＣｄＴｅ和ｎ型、ｐ型Ｈｇ０．５３Ｃｄ０．４７Ｔｅ界面的电学特性．ｎ型ＨｇＣｄＴｅＭＩＳ结构强反型区开始处的电导峰是表面处禁带态辅助的间接隧穿引起的；而ｐ型ＨｇＣｄＴｅＭＩＳ结构的强反型区电导出现两个振荡峰，是体陷阱辅助的价带电子到表面反型层二维子带的隧穿引起的，而耗尽区的电导峰则为界面态产生复合．指出ｐ型和ｎ型ＨｇＣｄＴｅＭＩＳ结构隧穿电导的差别是：ｐ型ＨｇＣｄＴｅＭＩＳ结构隧穿对表面处的禁带态不敏感．并用电导法研究ＣｄＴｅ／ＨｇＣｄＴｅ界面态在禁带中的分布，求得了界面态的时间常数和俘获截面     

μc—Si：H p—i—n薄膜太阳能电池中i层的设计分析

通过应用Ｓｃｈａｒｆｅｔｔｅｒ－Ｇｕｍｍｅｌ解法数值求解Ｐｏｉｓｓｏｎ方程，对热平衡μｃ－Ｓｉ：Ｈ ｐ－ｉ－ｎ薄膜太阳能电池进行计算机数值模拟。结果表明，光吸收体ｉ层或Ｐ型择杂都会在ｉ层中造成低场区而不利于光生载流子传输，指出μｃ－ＳｉＨ：ｐ－ｉ－ｎ太阳能电池制造中采用补偿μｃ－Ｓｉ：Ｈ薄膜充当吸收体ｉ层能提高长波（〉８００ｎｍ）载流子收集效率，从而增大电池的短路电流。     

Au／Sn与p—HgCdTe的欧姆接触

研究了双层金属结构Ａｕ／Ｓｎ与ｐ－ＨｇＣｄＴｅ上的接触电阻，实验测得Ａｕ／Ｓｎ与ｐ－Ｈｇ１－ｘＣｄＴｅ（ｘ＝０．２１７，０．４１）的经接触电阻，ρｃ（２９５Ｋ，７７Ｋ）为１０＾－２～１０＾４Ω．ｃｍ＾２将这种电板接触应用于Ｈｇ１－ｘＣｄｘＴｅ（ｘ＝０．２３）光伏器件，测得ｐｎ结Ｉ－Ｖ特性的正向斜率为１２．６Ω即电极接触电阻小于１２．６Ω。     

低暗电流InGaAs金属－半导体－金属光电探测器

首次采用双重肖特基势垒增强层技术，制作了ＩｎＧａＡｓ金属－半导体－金属光电探测器。实验结果表明：具有１５ｎｍ的ｐ－ＩｎＰ和１００ｎｍ的ＩｎＰ双重势垒增强层的器件，极大地减小了暗电流，最小达４．７ｎＡ（１０Ｖ），证明这是一种减小金属－半导体－金属光电探测器暗电流的有效途径     

低喑电流InGaAs金属—半导体—金属光电探测器

首次采用双重肖特基势垒增强层技术，制作了ＩｎＧａＡｓ金属－半导体－金属光电探测器。实验结果表明：具有１５ｍｍ的ｐ－ＩｎＰ和１００ｎｍ的ＩｎＰ双重势垒增强层的器件，极大地减少了暗电流，最小达４．７ｎＡ（１０Ｖ），证明这是一种减小金属－半导体－金属８光电探测器暗电流的有效途径。     

嵌入a—Si：H薄层的μc—Si／c—Si Pn异质结太阳能电池热平衡态特性的数值模拟

应用计算机数值模拟方法计算ｐ＾＋（μｃ－Ｓｉ：Ｈ）／ｎ（ｃ－Ｓｉ）及ｐ＾＋（μｃ－Ｓｉ：Ｈ）／ｉ（ａ－Ｓｉ：Ｈ＿／ｎ（ｃ－Ｓｉ）异质结太阳能电池中的电池中的电场强度分布,说明μｃ－Ｓｉ／ｃ－Ｓｉ异质结电池制造中μｃ－Ｓｉ：Ｈ膜厚选择,进而对嵌入ａ－Ｓｉ：Ｈ薄层的μｃ－Ｓｉ／ｃ－Ｓｉ异质结太阳能电池设计进行分析,包括ａ－Ｓｉ：Ｈ薄层ｐ型掺杂效应及本底单晶硅的电阻率选择,最后讨论μｃ－Ｓｉ／ｃ－Ｓｉ异     

Electrical and structural properties of epitaxial CdTe/HgCdTe interfaces

In this study, CdTe epilayers were grown by metalorganic chemical vapor deposition on epitaxial HgCdTe with the purpose of developing suitable passivation for HgCdTe photodiodes. Two types of CdTe layers were investigated. One was grown directly,in situ, immediately following the growth of HgCdTe. The second type of CdTe was grown indirectly, on top of previously grown epitaxial HgCdTe samples. In this case, the surface of the HgCdTe was exposed to ambient atmosphere, and a surface cleaning procedure was applied. The material and structural properties of the CdTe/HgCdTe interfaces were investigated using secondary ion mass spectroscopy, Auger electron spectroscopy, Rutherford back scattering, and x-ray double crystal diffractometry techniques. Electrical properties of the CdTe/HgCdTe heterostructure were determined by capacitance-voltage (C-V) characterization of Schottky barrier devices and metal insulator semiconductor devices. Also, a preliminary current-voltage characterization of n⁺ p photodiodes was performed. A theoretical model suitable for analysis of graded heterojunction devices was used for interpretation of C-V measurements.     

Influence of surface composition on back‐contact performance in CdTe/CdS PV devices

The atomic composition of the surface of the CdTe layer in a CdTe/CdS photovoltaic (PV) device has a significant influence on the quality of the electrical contact to this layer. This paper reports the results of a systematic study that correlates the composition of the back surface as measured with X‐ray photoelectron spectroscopy (XPS) with pre‐contact processing and device performance. We found that certain processing steps produce an oxide layer that degrades device performance by producing a metal – oxide – semiconductor (MOS) contact, rather than the intended metal – semiconductor, Schottky barrier contact. We also found that the as‐deposited CdTe film is cadmium‐rich for several hundred angstroms at the back surface. This n‐type layer may impede current flow for majority holes, degrading device performance. Published in 2000 by John Wiley & Sons, Ltd.     

Charge transport mechanisms in Schottky diodes based on low-resistance CdTe:Mn

CdTe:Mn crystals with a resistivity of ～1 Ω cm at 300 K and Schottky diodes based on them are investigated. The electrical conductivity of the material and its temperature variations are explained in terms of the statistics of electrons and holes in semiconductors with allowance for the compensation processes. The ionization energy and the degree of compensation of the donors responsible for the conductivity are determined. It is shown that, in the case of forward connection and low reverse biases, the currents in Au/CdTe:Mn Schottky diode are determined by generation-recombination processes in the space-charge region. At higher reverse biases (above 1.5–2 V) the excess current is caused by electron tunneling from the metal to the semiconductor, and at even higher voltages (>6–7 V) an additional increase in the reverse current due to avalanche processes is observed.     

n沟肖特基势垒隧穿晶体管特性研究

利用自主开发的蒙特卡罗器件模拟软件 ,对 n沟肖特基势垒隧穿晶体管 (SBTT)的输出特性和转移特性进行了模拟 ,详细分析了沟道区掺杂浓度 ,源漏硅化物区深度以及栅氧化层厚度对 SBTT特性的影响。     

Theoretical analysis of the quantum photoelectric yield in Schottky diodes

A detailed analytical calculation of the photoelectric quantum yield in Schottky diodes is presented. The transport of carriers in the surface space charge region is treated explicitly, taking account of photogeneration, diffusion and drift in the non-uniform electric field. Boundary conditions at the interface are expressed in terms of surface recombination velocity and emission velocity of excess carriers into the metal.It is shown that the metal-semiconductor interface strongly affects the collection efficiency of short wavelength generated electron-hole pairs. This effect basically originates in the emission flux of majority carriers into the metal.Current, charge carriers distributions and quantum yields are computed using the data of AuCdTe Schottky barriers.     

Ni/4H-SiC肖特基势垒二极管研制

采用微电子平面工艺,高真空电子束热蒸发金属Ni分别作肖特基接触和欧姆接触,二级场限环终端表面保护,研制出Ni/4H-SiC肖特基势垒二极管(SBD)。I-V特性测量说明,Ni/4H-SiCSBD有较好的整流特性,热电子发射是其主要的运输机理。反向击穿电压达1500V,理想因子为1.2,肖特基势垒高度为0.92eV。     

基于结终端扩展的4H-SiC肖特基势垒二极管研制

采用高真空电子束热蒸发金属Ni分别作肖特基接触和欧姆接触,离子注入形成结终端扩展表面保护,研制出Ni/4H-SiC肖特基势垒二极管(SBD)。I-V特性测量说明,Ni/4H-SiCSBD有较好的整流特性,热电子发射是其主要的运输机理。实验测量其反向击穿电压达1800V,且反向恢复特性为32ns。     

金属/有机高分子膜/n-InP肖特基势垒

本文介绍用有机高分子膜(LB膜和聚酰亚胺)代替n型InP肖特基势垒二极管中的薄氧化层,所得到的肖特基势垒二极管的势垒高度大于0.7eV,反向漏电流小于2.3×10~(-5)A/cm~2,性能稳定.还叙述了有机高分子膜的制备方法,电学测量结果,并与金属/薄氧化膜/n-InP肖特基势垒进行了比较,同时讨论了该法的优缺点.     

Characteristics of metal/sputtered CdTe/n-GaAs diode structures

Incorporation of a thin layer of r.f. sputtered CdTe between the metal and n-GaAs, has resulted in diode structures with MIS and Schottky barrier types C/V characteristics and low-current forward and reverse I/V characteristics. These structures have the potential to be useful in improving the performance of GaAs FET's for microwave and high speed applications.     

八毫米GaAs梁式引线肖特基势垒混频管

基于Pucel平面电容器模型和Berger平面电阻器的传输线模型(TLM),借助CAD技术,优化设计了平面型八毫米粱式引线混频管的几何参数,确定了关系到器件性能的几个关键尺寸 L_g、W_g、L_o和 L_b对总电容和串联电阻的影响.采用了类似于GaAs MESFET的制作工艺,并严格控制器件的几何参数.研制的八毫米混频管,典型结果是,在35GHz下,单管双边带噪声系数为4.8dB.