共查询到19条相似文献,搜索用时 140 毫秒
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文章详细介绍了多芯片组件(MCM)布线的四通孔(V4R)布线方法,它可以生成详细的布线结果,有利于节省成本和提高布线效率。V4R法可望得到更广泛的应用。 相似文献
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贯穿晶片的背面通孔已成为GaAsMMIC和功率MESFET的有效接地方式。本文介绍了利用Cl2/SiCl4作为反应气体,以正性光刻胶为掩模的反应离子刻蚀背孔工艺。利用该工艺刻蚀出的深孔具有倾斜的剖面和光滑的侧壁,孔的横向侧蚀小,在50mmGaAs圆片上获得了良好的均匀性和重复性。 相似文献
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多芯片组件(MCM)技术已是整机系统实现小型化、多功能化、高性能和高可靠不可缺少的技术途径。对MCM可靠性的研究也成为当前重要的研究课题。MCM可靠性的研究主要针对四个方面:(1)多层基板布线金属与隔离介质界面结构和反应状况;(2)层间互连通孔的互连可靠性;(3)环境应力研究;(4)表面组装焊接部位的应力分析。本文简述了国外就MCM-D在上述方面的研究概况,并提出我国多芯片组件可靠性研究的发展建议 相似文献
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采用电化学方法,对基板上的Al膜进行选择性阳极氧化,从而制得导带、通孔和介质,重复上述工序,便可制得多层布线基板。与常用多层布线基板,如MCM-C、MCM-D比较,它具有制作工艺简单独特、互连密度高,线径、间距和孔径更小,平面性好,绝缘电阻高等优点。 相似文献
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本文提出了一个深亚微米条件下的多层VLSMCM有约束分层层分配的遗传算法。该算法分为两步:首先进行超层分配,使各线网满足Crosstalk约束,且超层数目最少;然后进行各超层的通孔最少化二分层。与目前的层分配算法相比,该遗传算法具有目标全面,全局优化能力强等特点,是一种可应用于深亚微米条件下的IC CAD的有效分层方法。 相似文献
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本文提出了一种基于拓扑分析的多层通道布线算法。算法把整个布线过程分成拓扑分层和物理布线两个部分。拓扑分层利用线段交叠图及模拟退火算法解决线段分层及通孔最少化问题,物理布线过程引入虚拟走线道解决交叉问题,再利用轮廓线跟踪的方法来决定最终确定各线段的布线位置。算法还解决了多层布线分层的管脚约束问题和相邻约束问题。实验结果表明,这是一种有效的方法。 相似文献
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Heydari M.H. Tollis I.G. Chunliang Xis 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》1994,2(2):265-270
We present new algorithms for the layer assignment problem of multichip modules (MCM's). Our algorithms produce results that require between 70% and 25% of the number of layers required by the previous algorithms. We also present a new model for the problem that results in a better utilization of the routing area of the MCM, thus reducing the number of required layers even more. We provide lower and upper bounds on the performance of our algorithms which are tighter than the ones obtained before. Through our experimental results we show that the solutions obtained by our algorithms are close to the lower bounds 相似文献
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BGA/MCM进入现代组装技术的主流 总被引:1,自引:0,他引:1
文中分别介绍了BGA与MCM的概念,分类,发展现状,应用情况及发展趋势等。BGA与MCM是现代组装技术的两个新概念,是SMT(表面贴装技术)与SMD(表面贴装元器件)的发展和革新,从其产生到现在,发展不过几年的时间。电子界的权威士对BGA的发展很乐观,他们认为BGA将成为高密度、高性能、多功能及高I/O引线射封装的最佳选择。而MCM将更多地应用BGA,逐渐降低成本,减小尺寸和重量,进一步提高性能, 相似文献
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Multichip modules (MCM's) have been actively developed in recent years. They are expected to provide high-performance systems by packing bare chips at a high density. In particular, a thin-film interconnect substrate that can accommodate higher wiring capacity in a few layers is a new option for coping with high pin count and fine pad pitch VLSI's. MCM's require various kinds of technologies including the fabrication processes of interconnect substrates, chip connection methods, electrical design, thermal management, known good die (KGD), and so on. The state of the art of MCM technologies is reviewed and future directions are discussed 相似文献
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Chang Yifeng Yang Yintang 《电子科学学刊(英文版)》2006,23(5):741-744
This paper presents a timing-driven MultiChip Module (MCM) routing algorithm considering crosstalk, which maximizes routing density while minimizing vias and total wire length. The routing algorithm allows a more global solution as well as the incorporation of more accurate crosstalk modeling. In addition, various time domain characteristics of MCM are analyzed in this contribution. A deembedding technique for the S-parameter calculation is presented and functions for the time-domain signals are investigated in order to decrease the computation time. Routing results show that the proposed algorithm consistently produces the better results than other previously proposed routers while offering flexibility for future incorporation of noise and delay constraints. 相似文献
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As analog and mixed-signal (AMS) circuitry gains increasing portions in modern SoCs, automatic analog routing is becoming more and more important. However, routing for analog circuits has always been an extremely challenging task due to complicated electrical and geometrical constraints. Due to these constraints, current analog routers often fail to obtain a routing solution that the designer wants. To incorporate the designer׳s expertise during routing, a customized real-time interactive analog router is attracting increasing concerns in industry.This paper presents a fast customized real-time interactive analog router called SIAR. A key feature of SIAR is that it allows for real-time interactions between the router and the designer. The designer can try different guiding points by moving the cursor in the user window and SIAR will return and display the corresponding routing solution in real-time, such that the designer could choose the most satisfactory one. The guiding points are very important for the designer to obtain satisfactory routing solutions, even for routing solutions with analog matching constraints by setting symmetric guiding points. A new splitting graph based routing model is presented to efficiently search the routing path and record the number of turns/vias during searching by efficient tile splitting operations. SIAR supports different routing modes such as point-to-point, point-to-module and module-to-module. An efficient connecting point selection method is presented such that an optimal routing solution is preserved when connecting to a module. Different design rules such as variable wire and via width/spacing rules, along with the same-net spacing rules, are supported in SIAR. Moreover, a global routing stage is presented to speedup the routing process for large designs. Experimental results are promising. 相似文献