A Design Style for VLSI CMOS

CMOS is an attractive technology for the realization of VLSI systems. However conventional static CMOS design techniques lead to circuits which are slower and much less densely packed than equivalent NMOS circuits. After a brief review of precharge-discharge techniques, a novel method for designing clocked dynamic CMOS is described. This uses a four-phsse clocking scheme that is free from race and charge-sharing problems and results in faster, more compact layouts. A test chip and a full custom 25 000 transistor serial signal processing chip have been designed using this technique. Results obtained by probing the test ship are presented.     

A novel fully integrated device dedicated to ECG signal measurement

This paper describes two novel fully integrated circuits implemented in standard 0.35 μm CMOS technology dedicated to ECG signal measurement. Many specific problems related to this kind of signal are discussed. Pertinent solutions, such as high pass filtering, offset cancellation, common mode rejection, low pass filtering and capacitive coupling between different stages are proposed.     

A CMOS digitally programmable filter technique for VLSI applications

A novel technique for designing analog CMOS integrated filters is proposed. The technique uses digitally controlled current amplifiers (DCCAs) to provide precise frequency and/or gain characteristics that can be digitally tuned over a wide range. This paper provides an overview of the possibilities of using the DCCA as the core element in programmable filters. In mixed analog/digital systems, the digital tuning feature of the proposed approach allows direct interfacing with the digital signal processing (DSP) part. Basic building blocks such as digitally programmable amplifiers, integrators, and simulated active inductors are given. Systematic designs of second-order filters are presented. Fully differential architectures of the proposed circuits are developed. Experimental results obtained from 0.5 μm standard CMOS chips are provided.     

Architecture and design of a 500-MHz gallium-arsenide processingelement for a parallel supercomputer

The design of the processing element of GASP, a GaAs supercomputer with a 500-MHz instruction issue rate and 1-GHz subsystem clocks, is presented. The novel, functionally modular, block data flow architecture of GASP is described. The architecture and design of a GASP processing element is then presented. The processing element (PE) is implemented in a hybrid semiconductor module with 152 custom GaAs ICs of eight different types. The effects of the implementation technology on both the system-level architecture and the PE design are discussed. SPICE simulations indicate that parts of the PE are capable of being clocked at 1 GHz, while the rest of the PE uses a 500-MHz clock. The architecture utilizes data flow techniques at a program block level, which allows efficient execution of parallel programs while maintaining reasonably good performance on sequential programs. A simulation study of the architecture indicates that an instruction execution rate of over 30,000 MIPS can be attained with 65 PEs     

A Processor-In-Memory Architecture for Multimedia Compression

This paper presents the design and development of a novel, low-complexity processor-in-memory (PIM) architecture for image and video compression. By integrating a novel-processing element with SRAM, bandwidth is improved and latency is greatly reduced. This paper also presents PIM design techniques for reduced power, area, and complexity for rapid deployment and reduced cost. A design methodology is presented and followed by an analysis of the processing element performance and capabilities. The proposed datapath solution delivers between 2 to 40 times higher performance compared to other presented solutions. The architecture executes a discrete cosine and wavelet transforms achieving up to 40% higher throughput per watt and occupying as little as 0.9% area compared to a commercial digital signal processing and other application-specified integrated circuit implementations while maintaining precision. A comprehensive comparative analysis is also provided. The proposed processor-in-memory is implemented in 1.8-V 0.18-mum CMOS technology and operates with a 300-MHz clock     

Integrated Circuit Biosensors Using Living Whole-Cell Bioreporters

A low-power CMOS bioluminescent bioreporter integrated circuit (BBIC) is designed and fabricated for use in electronic/biological chemical sensing. The bioreporters are placed on a CMOS integrated circuit (IC) that detects bioluminescence, performs signal processing and produces a digital output pulse with a frequency that is proportional to the concentration of the target substance. The digital output pulse that contains the sensor information can then be transmitted to a remote location either wirelessly or via a data cable. The basic building blocks of the integrated circuit are the microluminometer and the transmitter. The microluminometer includes an integrated photodetector and a signal processor and is housed in a rugged inexpensive package that can be used in many remote applications in hazardous environmental monitoring. The total power consumption of the entire signal processing circuitry including the photodiodes is 3 mW from a 3.3-V power supply. This is lowered by a factor of 3 when compared to previous versions of the BBIC. In addition, it also integrates all features of detection, processing and data transmission into one small element. The bioreporter typically contains the luxCDABE reporter genes. The close proximity of the bioreporter and the sensing element eliminates the need for complex instrumentation to channel light from the bioreporters to the microluminometer. This paper presents an integrated CMOS microluminometer realized in 0.35-mum CMOS process and optimized for the detection of low-level bioluminescence as part of the BBIC. A flow-through test system was designed to expose the BBIC system composed of the microluminometer and the bioreporter Pseudomonas fluorescens 5RL to salicylate for determination of analytical benchmark data. The results obtained from the experiment are currently being used to study enclosures and micro-environment configurations for field-deployable BBICs for environmental monitoring     

A deformable mirror-based optical beamforming system for phasedarray antennas

Microwave carrier generation along with the signal processing required for dynamic beamsteering of a high-resolution phased array antenna with an arbitrary radiation pattern is accomplished using optical components. It is shown that a deformable mirror type spatial light modulator can establish a truly arbitrary continuous optical phasefront which is directly converted to spatial RF phase information by an optical heterodyne system. Experimental results simulating the performance of the actual system are presented. A spatially integrated optical implementation providing mechanical stability and essentially eliminating the drift problems usually encountered in free space systems is presented     

60GHz single-chip CMOS digital radios and phased array solutions for gaming and connectivity

In this paper, we present four examples of highly integrated 60 GHz single-chip CMOS 90 nm digital radios and phased array solutions. These solutions include for the first time digital-to-analog/analog-to-digital conversion and embedded multi-gigabit mixed signal modem requiring no external processing. This convergence of 60 GHz CMOS digital radio, low power multi-gigabit mixed-signal processing and digital signal processing on a single chip offers the lowest energy per bit transmitted wirelessly at multi-gigabit rate to meet the very stringent low-power specifications for battery operated consumer electronic portable devices. Layout and temperature dependent 60 GHz CMOS 90 nm model development and critical high performance analog and mixed building blocks are presented as fundamental enablers for single chip integration. The designs have been optimized for robustness against process variation and temperature, and verified by measurement results.     

A PCM transcoder circuit and remote metering generator for line circuit applications

The two functions are implemented in a custom integrated circuit (TCF). The system, circuit, and technological aspects of the design are described. The TCF chip performs transcoding from/to 13-bit linear to/from 8 bit, A-law or /spl mu/-law companded PCM, for 32 multiplexed channels. Every channel is transcoded, in both directions, every 125 /spl mu/s. A second function of the device is the generation of metering signal bursts free of audible clicks. The metering frequency is selectable at 12 or 16 kHz. In order to achieve low power consumption and minimal area, all the circuitry is implemented using fully dynamic CMOS.     

Entwurf gemischt analog-digitaler Systeme

Today mainly submicron CMOS and BiCMOS technologies are used for the design of mixed analogue-digital applicationspecific integrated circuits (ASIC). This allows to integrate complete systems. Overall system costs are reduced and the reliability of the complete system can be improved. Today’s electronic systems often contain sensors to convert non-electric signals followed by electronic amplifiers, filters, analogue-to-digital converters and digital signal processing. The advantages of analogue and digital signal processing can be integrated on a single IC and for some applications it is even possible to include the sensor on the silicon chip.     

Current-mode CMOS integrated circuits for analog computation and signal processing: A tutorial

This paper presents an overview of design techniques for a broad range of current-mode analog integrated circuits implemented in CMOS technology at a tutorial level. Primarily, emphasis is placed on circuit configurations, first-order analysis, and approximate design equations for analog integrated circuits operating in current domain for signal computation and processing applications.     

Time Delay Integration and In-Pixel Spatiotemporal Filtering Using a Nanoscale Digital CMOS Focal Plane Readout

A digital focal plane array (DFPA) architecture has been developed that incorporates per-pixel full-dynamic-range analog-to-digital conversion and orthogonal-transfer-based realtime digital signal processing capability. Several long-wave infrared-optimized pixel processing focal plane readout integrated circuit (ROIC) designs have been implemented, each accommodating a 256 times 256 30-mum-pitch detector array. Demonstrated in this paper is the application of this DFPA ROIC architecture to problems of background pedestal mitigation, wide-field imaging, image stabilization, edge detection, and velocimetry. The DFPA architecture is reviewed, and pixel performance metrics are discussed in the context of the application examples. The measured data reported here are for DFPA ROICs implemented in 90-nm CMOS technology and hybridized to Hg_xCd_1-xTe (MCT) detector arrays with cutoff wavelengths ranging from 7 to 14.5 mum and a specified operating temperature of 60 K-80 K.     

Current-mode signal processing implementation in HV SoI integrated systems

The paper presents and discusses possibilities and potential of current-mode based signal processing in high-voltage (HV) integrated systems, including current-mode functional block implementation into signal path of HV voltage-mode circuits. The paper is mostly focused on analog circuitry, implemented with the use of SoI processes. Discussion is based on the range of circuit solutions previously devised by authors and presently combined to present cumulated potential of current-mode approach in high-voltage (HV) integrated circuits. Analysis of the referenced research conducted by the authors of the paper, points out that in HV integrated systems, there are application areas well suited for current-mode processing implementation rather than the classic voltage-mode approach. Simplicity and consistency of HV current-mode functional blocks are presented, along with fitness of current-mode circuits for convenient implementation into HV SoI integrated circuits, with very limited loss of operation quality as compared to corresponding low-voltage functional blocks. Means of implementing current-mode circuits into HV voltage-mode systems are discussed.     

Semi-static threshold-triggered delay elements for low power operation

Delay elements are widely used in mixed signal integrated circuits in order to meet design-specific timing requirements. Generally delays are generated by lengthening the transition times of the input signal which is subsequently restored. Slow transition times however, results in prolonged short-circuit current duration at the signal restoration stage, not only increasing the overall power consumption of the system but also limiting the usable output delay range. This paper presents a novel CMOS semi-static threshold-triggered delay element architecture that minimizes the short-circuit current over a wide output delay range. The architecture can also incorporate conventional delay elements to improve their performance. The presented delay element is fabricated in a commercial 0.35 μm CMOS technology and the measurement results show significant improvements in output delay range and average power consumption over other conventional delay elements.     

Analog CMOS circuit design and characterization for optical coherence tomography signal processing

We have developed a custom analog CMOS circuit to perform the signal processing for an optical coherence tomography imaging system. The circuit is realized in a 1.5 /spl mu/m low-noise analog CMOS technology. The circuitry extracts the Doppler frequency from the signal and electrically mixes this with the original signal to provide a filtered A-scan. The circuitry was used to produce a two-dimensional image of an onion.     

CMOS current-controlled current differencing transconductance amplifier and applications to analog signal processing

This article presents design of a basic current-mode building block for analog signal processing, named as current-controlled current differencing transconductance amplifier (CCCDTA). Its parasitic resistances at two current input ports can be controlled by an input bias current. Owing to working in current-mode of all terminals, it is very suitable to use in a current-mode signal processing, which is continually more popular than a voltage one. The proposed element is realized in a CMOS technology and is examined the performance through PSPICE simulations. They display usability of the new active element, where the maximum bandwidth is 311 MHz. The CMOS CCCDTA performs low power consumption and tuning over a wide current range. In addition, some examples as a current-mode universal biquad filter, floating inductance simulator and quadrature oscillator are included. They occupy only single CCCDTA.     

Design of the processing core of a mixed-signal CMOS DTCNN chip for pixel-level snakes

This paper introduces the processing core of a full-custom mixed-signal CMOS chip intended for an active-contour-based technique, the so-called pixel-level snakes (PLS). Among the different parameters to optimize on the top-down design flow our methodology is focused on area. This approach results in a single-instruction-multiple-data chip implemented by a discrete-time cellular neural network with a correspondence between pixel and processing element. This is the first prototype for PLS; an integrated circuit with a 9/spl times/9 resolution manufactured in a 0.25 -/spl mu/m CMOS STMicroelectronics technology process. Awaiting for experimental results, HSPICE simulations prove the validity of the approach introduced here.     

Analog VLSI Circuit Implementation of an Adaptive Neuromorphic Olfaction Chip

In this paper, we present the analog circuit design and implementation of the components of an adaptive neuromorphic olfaction chip. A chemical sensor array employing carbon black composite sensing materials with integrated signal processing circuitry forms the front end of the chip. The sensor signal processing circuitry includes a dc offset cancellation circuit to ameliorate loss of measurement range associated with chemical sensors. Drawing inspiration from biological olfactory systems, the analog circuits used to process signals from the on-chip odor sensors make use of temporal "spiking" signals to act as carriers of odor information. An on-chip spike time dependent learning circuit is integrated to dynamically adapt weights for odor detection and classification. All the component subsystems implemented on chip have been successfully tested in silicon     

VLSI implementation of a signal recognition and code acquisitionalgorithm for CDMA packet receivers

The widespread application of direct-sequence spread-spectrum code division multiple access (DS/SS-CDMA) to wireless communication systems asks for ever faster and more reliable real-time signal processing operations to be performed by highly integrated and low-power consumption digital receivers. One of the most critical signal processing tasks to be performed by the DS/SS-CDMA receiver is signal presence detection and code epoch estimation. This paper deals with the design and realization of an application-specific integrated-circuit (ASIC) for fast signal recognition and code acquisition (SR/CA) in packet DS/SS-CDMA receivers operating in a satellite or terrestrial radio network. In particular, we show how a parallel acquisition circuit can be effectively implemented on a single-chip with a 1.0-μm CMOS technology according to the specifications of the ARCANET Ku-band CDMA VSAT satellite network sponsored by the European Space Agency (ESA). It is shown that the ASIC performance closely follows analytical predictions     

Bridging the gap between signal and power

Signal processing has been used in many different applications, including electric power systems. This is an important category, since a wide variety of digital measurements is available and data analysis is required to deliver diagnostic solutions and correlation with known behaviors. Measurements are taken at numerous locations, and the analysis of data applies to a variety of issues in ? power quality (PQ) and reliability ? power system and equipment diagnostics ? power system control ? power system protection. This article focuses on problems and issues related to PQ and power system diagnostics, in particular those where signal processing techniques are extremely important. PQ is a general term that describes the quality of voltage and current waveforms. PQ problems include all electric power problems or disturbances in the supply system that prevent end-user equipment from operating properly. Examples of voltage and current variations that can result in PQ problems include voltage interruptions, long- and short-duration voltage variations, steady-state research opportunities that use the measured voltages and currents to indicate possible equipment and system problems (referred to as equipment diagnostics).