一种基于SoC的MPEG-4视频解码加速器

实现了一种应用于系统芯片（SoC）的MPEG-4视频解码加速器。该解码器可完成MPEG-4解码中计算量最大的离散余弦变换（IDCT）、反量化（inverse quantization）和运动补偿叠加（reconstruction）。本文通过算法、总线接口、存储器结构以及硬件开销方面的优化,使得在满足MPEG-4实时解码的基础上,加速器占用SoC系统芯片的总线带宽和硬件面积尽量的小,并有利于存储器的复用。经实验验证,本设计可以对MPEG-4简单层（simple profile）实时解码。     

片上总线WI SHBONE在多媒体处理器SoC中的开发与设计

论文先简要论述了片上总线协议及其在可重用SoC设计中的主要作用，并以基于WISHBONE片上总线设计的Flash Memory控制器设计为例，说明基于WISHBONE片上总线的SoC的可重用设计方法的可行性、科学性?     

总线监视器的设计

随着集成电路设计规模的不断增加，传统的验证方法学由于无法提供足够的能力来检查系统所有可能功能的正确性，已经不能满足SoC验证的需求。验证重用方法学是解决这一问题的有效途径。在SoC的验证过程中．利用总线监视器对片上总线上发生的事务进行实时监视，并将监视结果以机器可读的格式显示出来，从而可以帮助验证工程师有效地判断数据传输的正确性，达到验证单个模块和系统功能的目的。本文提出了一种SoC功能。验证平台中总线监视器的设计方法，并给出了具体的实现过程。     

低翻转率的SoC总线组合编码算法

为降低SoC总线功耗，避开现有总线编码技术在应用上的局限，提出了一种SoC总线编码算法。算法基于总线上IP可复用的观点，采用分组BI码和TO码各自的优点，在维持SoC总线功能基本不变的同时，减少数据线和地址线的电平翻转。最后的实验结果表明：组合编码算法可以将SoC总线的平均功耗下降7．41％，是一种有效且适用于SoC总线的低功耗算法。     

HDTV SoC平台中存储器控制及其VLSI优化

在分析视频解码标准硬件实现要求的基础上，提出了SoC系统结构和SDRAM接口控制器的设计策略，包括冲突调度和面向提升带宽利用率的优化设计。并配置了一个二级请求缓冲池，配合固定优先级策略，解决了共享设备总线冲突问题；提出bank交叠方法隐藏读写等待时间，以达到提高带宽利用率的目的；另外，还用合并空闲状态的方法实现硬件可重用。     

零翻转编码地址总线SoC低功耗设计

本文分析了SoC设计中大电容负载的地址总线低功耗设计方法。利用地址总线零翻转编码和解码技术，有效地减少了SoC地址总线活动，降低了SoC芯片和系统的功耗。同时，应用于实际的SoC设计中，验证了它的功能和适用范围。     

一种媒体增强的可配置RISC微处理器核设计

针对嵌入式多媒体应用，设计了一种媒体增强的可配置微处理器核RISC32。研究了媒体增强扩展．流水线控制策略，旁路技术以及异常处理等。RISC32采用参数化和模块化设计方法，具有较强的可配置性。在Xilinx X2CV3000 FPGA上通过了指令集仿真，并进行了基于RISC32的MPEG-4 AAC音频实时解码实验．表明该RISC核能够方便地应用于片上系统（SoC）。     

基于总线功能模型的SoC仿真加速技术

SoC是IC设计的发展趋势,而随着SoC的日趋复杂,对系统仿真带来了越来越艰巨的挑战,基于EDA厂商提供的传统仿真环境已经不能充分满足SoC的开发需求,针对此问题提出了基于总线功能模型的仿真加速策略,测试结果表明,提出的技术策略可获得45%的仿真性能提升。     

基于3G SIM卡SoC芯片设计的AMBA总线的精简策略

AMBA总线是SoC设计中普遍采用的总线架构,它对许多具体的设计项目往往显得过于庞大,结合3G SIM卡SoC芯片的设计,研究了AMBA总线架构的若干精简策略,提出了一些对总线进行裁剪的参考方法,经过AHB VIP验证环境表明结果可行.该方法对基于AMBA架构的SoC芯片设计有着一定的参考意义.     

基于SystemC的AMBA总线模型的构建与验证

针对SoC设计中的时间瓶颈，利用SystemC设计语言根据AMBA规范建立了事务级总线模型，并将MP3解码器和控制器作为主设备接入该模型，验证本模型的可用性与有效性，试验结果表明该模型可以有效地在系统层次对SoC芯片的集成进行设计验证，加快SoC系统的设计速度，且能做到时钟精确。     

FABSYN: floorplan-aware bus architecture synthesis

As system-on-chip (SoC) designs become more complex, it is becoming harder to design communication architectures to handle the ever increasing volumes of inter-component communication. Manual traversal of the vast communication design space to synthesize a communication architecture that meets performance requirements becomes infeasible. In this paper, we address this problem by proposing an automated approach for floorplan-aware bus architecture synthesis (FABSYN) to synthesize cost-effective, bus-based communication architectures that satisfy the performance constraints in a design. Our synthesis approach incorporates a high-level floorplanning and wire delay estimation engine to evaluate the feasibility of the synthesized bus architecture and detect bus cycle time violations early in the design How, at the system level. We present case studies of network communication SoC subsystems for which we synthesized bus architectures, detected and eliminated timing violations, and generated core placements in a matter of hours instead of several days for a manual effort.     

Performance Analysis for MPEG‐4 Video Codec Based on On‐Chip Network

In this paper, we present a performance analysis for an MPEG‐4 video codec based on the on‐chip network communication architecture. The existing on‐chip buses of system‐on‐a‐chip (SoC) have some limitation on data traffic bandwidth since a large number of silicon IPs share the bus. An on‐chip network is introduced to solve the problem of on‐chip buses, in which the concept of a computer network is applied to the communication architecture of SoC. We compared the performance of the MPEG‐4 video codec based on the on‐chip network and Advanced Micro‐controller Bus Architecture (AMBA) on‐chip bus. Experimental results show that the performance of the MPEG‐4 video codec based on the on‐chip network is improved over 50% compared to the design based on a multi‐layer AMBA bus.     

AHB总线分析及从模块设计

AMBA总线结构广泛应用于片上系统设计中,其中AHB总线用于系统中高性能、高时钟速率模块间通信。AHB总线接口设计技术是片上系统设计的基本技术。AHB总线接口设计划分为主控模块接口设计及从模块接口设计。在详细论述AHB总线工作原理后,重点介绍了SRAM从模块AHB接口设计,包括SRAM读写控制信号的时序要求,传输操作时插入等待状态的方法,以及响应信号的产生。     

Exploiting intellectual properties with imprecise design costs for system-on-chip synthesis

This paper presents an intellectual property (IP)-based system-on-chip (SoC) synthesis framework focusing on how to select IPs from different sources and how to integrate the selected IPs using on-chip buses. In order to synthesize an on-chip bus-based SoC architecture using IPs with imprecise design costs, we propose a possibilistic mixed integer linear programming (PMILP) model, which is converted into an equivalent mixed integer linear programming (MILP) model without increasing the computational complexity. Then, the equivalent MILP model is solved to decide whether each IP is selected or not, and to locate the selected IP on the optimal on-chip bus of a hierarchical bus architecture that consists of on-chip buses with different bus attributes. Experimental results on an MP3 decoding system show that the IP-centric design space with uncertainty can be successfully explored using the proposed scheme.     

高效能,低功耗DDR2控制器的硬件实现

随着SoC芯片内部总线带宽的需求增加,内存控制器的吞吐性能受到诸多挑战。针对提升带宽性能的问题,可以从两个方面考虑,一个办法是将内存控制器直接跟芯片内部几个主要占用带宽的模块连接,还要能够对多个通道进行智能仲裁,让他们的沟通不必经过内部的AMBA总线,甚至设计者可以利用高效能的AXI总线来加快SoC的模块之间的数据传输。另一个办法就是分析DDR2SDRAM的特性后设计出带有命令调度能力的控制器来减少读写次数,自然就能够降低SoC芯片的功耗,为了节能的考虑还要设计自动省电机制。本文为研究DDR2SDRAM控制器性能的提升提供良好的思路。     

LotteryBus的设计与实现

为了提高SoC内部总线的性能,优化总线架构.文章提出了一种新颖的LotteryBus总线机制.通过将其与静态优先级及时分复用总线进行比较,介绍了它的特点及其仲裁机制.并且设计和实现了一个4-Masters的LottervBus用于龙芯SoC内部高速总线的改进,功能仿真和FPGA验证证明这一总线机制的可行性和正确性.     

SoC片上总线技术的研究

在SoC设计中,经常会遇到一些问题,包括IP核移植性、设计复用、设计验证,以及公共设计平台的搭建。如何有效地解决这些问题,使得设计SoC系统就像设计微机系统那样方便快捷,这就是片上总线系统提出的目的。本文通过对AMBA, AVALON, OCP,WISHBONE等SoC总线的比较,分析了SoC片上总线技术。     

SoC interconnection protection through formal verification

The wide adoption of third-party hardware Intellectual Property (IP) cores including those from untrusted vendors have raised security concerns for system designers and end-users. Existing approaches to ensure the trustworthiness of individual IPs rarely consider the entire SoC design, especially the IP interactions through SoC bus. These methods can hardly identify malicious logic (or design flaws) distributed in multiple IPs whereas individual IPs fulfill security properties and can pass the security testing/verification. One possible solution is to treat the SoC as one IP core and try to verify security properties of the entire design. This method, however, suffers from scalability issues due to the large size of SoC designs with multiple IP cores integrated. In this paper, we present a scalable SoC bus verification framework trying to verify the security properties of SoC bus implementation where the bus protocol plays the role of the golden reference. More specifically, finite state machine (FSM) models will be constructed from the bus implementation and the trustworthiness will be verified based on the property set derived from the bus protocol and potential security threats. Along with IP level formal verification solutions, the proposed framework can help ensure the security of large-scale SoCs. Experimental results on ARM AMBA Bus demonstrate that our approach is applicable and scalable to prevent information leakage and denial-of-service (DoS) attack by verifying security properties.