共查询到19条相似文献,搜索用时 93 毫秒
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分析了MPEG-视频编解码系统结构,在此基础上给出一个实时的MPEG-4视频编解码系统架构,并对解码的具体步骤进行了详细分析,预测了MPEG-4的编解码芯片的趋势. 相似文献
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文章设计了一个低功耗、可复用、MPEG-1/2 LayI/Ⅱ/Ⅲ音频解码IP核。该IP核主要应用于包含一个CPU的嵌入式多媒体处理系统。该IP核包含了一个Software-Core和一个Hardware-Core,在两者的配合下,可以在非常低的时钟频率下高精度解码MPEG-1/2 LayI/Ⅱ/Ⅲ音频码流。在实时解码128kbps/44.1kHz MPEG-1/2LayerⅡ码流时,Hardware-Core工作在5.6448MHz,Software-Core工作在8MHz。文章最后给出另一个该IP在典型SoC系统中的应用。Hardware-Core在CMOS0.18μm工艺下,芯片面积为1520μm×1280μm。 相似文献
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介绍了一种实时MPEG-2以太网传输系统的设计方案,它由硬件MPEG-2编/解码卡和基于ARM处理器的嵌入式系统卡构成,前者用于视音频的实时压缩编码和解码,后者将MPEG-2数据流进行IP封装和解封装,还分析了IP网络传输对接收端MPEG-2解码视音频的影响,并设计了一些测评方法对系统进行了相关测评. 相似文献
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基于DM642DSP的MPEG-4视频解码算法优化设计 总被引:1,自引:4,他引:1
讨论并实现了基于DSP的MPEG-4视频实时解码算法。首先系统级优化算法,修改适于DSP的数据结构以减小算法对存储器的要求,然后有效分配片上核心内存,针对DSP自身的特点,对EDMA、缓存Cache、线性汇编优化和软件流水及CCS优化工具等方面做专门优化。实验结果证明,该优化算法可实现多路视频图像的实时解码,在码流300 kb/s、CIF分辨率I、BP模式条件下,MPEG-4解码算法速度可达190-200 f/s。 相似文献
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MP3是诸如音乐播放器,移动电话等移动设备上最为流行的高质量音频压缩格式.描述了在SoC芯片AS3310D上,基于通用软件优化技术和芯片上特有的DMA控制器,对MP3软件解码器的优化,最终获得了42.7%性能的提高和38.8%存储空间的节省. 相似文献
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高效能,低功耗DDR2控制器的硬件实现 总被引:1,自引:0,他引:1
随着SoC芯片内部总线带宽的需求增加,内存控制器的吞吐性能受到诸多挑战。针对提升带宽性能的问题,可以从两个方面考虑,一个办法是将内存控制器直接跟芯片内部几个主要占用带宽的模块连接,还要能够对多个通道进行智能仲裁,让他们的沟通不必经过内部的AMBA总线,甚至设计者可以利用高效能的AXI总线来加快SoC的模块之间的数据传输。另一个办法就是分析DDR2SDRAM的特性后设计出带有命令调度能力的控制器来减少读写次数,自然就能够降低SoC芯片的功耗,为了节能的考虑还要设计自动省电机制。本文为研究DDR2SDRAM控制器性能的提升提供良好的思路。 相似文献
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Nam Ling Nien-Tsu Wang 《Broadcasting, IEEE Transactions on》2002,48(4):353-360
We present a scheme for real-time digital HDTV video decoding suitable for DVB or ATSC set-top boxes. Our technique is based on a dual decoding datapath controlled in two fixed-scheduling combinations with an efficient memory interface scheme for anchor pictures. Unlike other decoding approaches such as the slice bar decoding method and the crossing-divided method, our scheme reduces memory access contention problem to achieve real-time HDTV decoding without a high cost in overall decoder buffers, architecture, and bus. Our simulation shows that with a relatively low rate 81 MHz clock, our decoder can decode MPEG-2 MP@HL HDTV in real-time, based on a video format of 1920 /spl times/ 1080 pixels/frame at 30 frames/s, at a bit rate of 18-22 Mbps. 相似文献
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当前主流片上总线协议—AHB存在访存带宽利用率较低的问题.本文基于SoC内DMA传输较多的特点,提出一种新的优化设计:在内存控制器内部增加MCS-DMA模块,并通过驱动程序将MCS-DMA模块与目标DMA传输绑定. 一方面实现数据预取,提升单个DMA传输时的总线带宽利用率;另一方面使访存请求在内存控制器内部流水化完成,提升多个DMA并发时的总线带宽利用率.将该设计应用到北大众志SK SoC后,单个DMA传输时的总线带宽利用率提升至100%,多个DMA并发时的总线带宽利用率从33.3%提升至85.5%,而芯片设计面积仅增加2.9%. 相似文献
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Byoung-Woon Kim Chong-Min Kyung 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2002,10(3):240-252
This paper presents an intellectual property (IP)-based system-on-chip (SoC) synthesis framework focusing on how to select IPs from different sources and how to integrate the selected IPs using on-chip buses. In order to synthesize an on-chip bus-based SoC architecture using IPs with imprecise design costs, we propose a possibilistic mixed integer linear programming (PMILP) model, which is converted into an equivalent mixed integer linear programming (MILP) model without increasing the computational complexity. Then, the equivalent MILP model is solved to decide whether each IP is selected or not, and to locate the selected IP on the optimal on-chip bus of a hierarchical bus architecture that consists of on-chip buses with different bus attributes. Experimental results on an MP3 decoding system show that the IP-centric design space with uncertainty can be successfully explored using the proposed scheme. 相似文献
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In this paper, an architecture for real-time digital HDTV video decoding is presented. Our architecture is based on a dual decoding datapath controlled in a fixed schedule with an efficient write-back scheme for anchor pictures. The decoding datapath is synchronized at the block (8 × 8 pixels) level. Unlike other decoding approaches such as the slice bar decoding method and the cross-divide method, our scheme reduces memory access contention problem to achieve real-time HDTV decoding without a high cost in overall decoder buffers, architecture, and bus. In comparison to data-flow approaches, our method eliminates the complexity associated with tagged data operations. Our anchor picture storage is organized to minimize page-breaks during memory accesses. Simulation shows that with a relatively low rate 81 MHz clock, our decoder can decode MPEG-2 MP@HL HDTV in real-time, based on an ATSC video format of 1,920 × 1,080 pixels/frame at 30 frames/s, at a bit rate of 18 to 20 Mbps. 相似文献