低踢回噪声锁存比较器的分析与设计

设计了一种低踢回噪声锁存比较器，着重分析和优化了比较器的速度和失调电压。在0.35μm CMOS工艺条件下，采用Hspice对电路进行了模拟。结果表明，比较器的最高工作频率为200MHz，分辨率在6位以上，灵敏度为0．3mV；在2．5V电源电压下，功耗为70μW。     

一种高速高精度比较器的设计

基于预放大锁存快速比较理论,提出了一种高速高精度CMOS比较器的电路拓扑.该比较器采用负载管并联负电阻的方式提高预放大器增益,以降低失调电压.采用预设静态电流的方式提高再生锁存级的再生能力,以提高比较器的速度.在TSMC0.18μm工艺模型下,采用Cadence Specture进行仿真.结果表明,该比较器在时钟频率为1GHz时,分辨率可以达到0.6mV,传输延迟时间为320ps,功耗为1mW.     

高速CMOS预放大-锁存比较器设计

基于预放大-锁存理论，提出了一种带1级预放大器的高速CMOS锁存比较器电路拓扑结构；阐述了其传输延迟时间、回馈噪声和输入失调电压的改进方法。采用典型的0．35μm／3．3V硅CMOS工艺模型，通过Cadence进行模拟验证，得到其传输延迟时间380ps，失调电压6．8mV，回馈噪声对输入信号产生的毛刺峰峰值500μV，功耗612μw。该电路的失调电压和回馈噪声与带两级(或两级以上)CMOS预放大锁存比较器的指标相近，且明显优于锁存比较器。其功耗和传输延迟时间介于两种比较器之间．该电路可用于高速A／D转换器模块与IP核设计。     

基于0.6μm CMOS工艺应用在高速ADC工作频率300MHz的高速电压比较器设计

高速比较器是高速模数转换电路的关键环节.本文综合考虑了比较器的传输延时、失调电压等因素,分析了前置放大器和比较锁存电路的结构,在此基础上设计了一个基于CSMC 0.6 μm CMOS工艺、适合于高速ADC的高速电压比较器.仿真结果表明:比较器工作频率为300 MHz以上,工作电流约为3.3 mA,上升延时为993 ps,下降延时为932 ps,失调电压约为7.46 mV.该比较器可以在高速模数转换电路中应用.     

一种用于数字功放的低功耗宽输入电压比较器

设计了一种适用于数字功率放大器应用的全差分低功耗宽输入CMOS电压比较器.采用TSMC 0.18μm/3.3V CMOS工艺模型,用Cadence软件进行模拟仿真,比较器低频增益81.2dB,输入共模电压范围1.4~3.3V,整个电路的静态功耗仅248.6μW.运用该结构的比较器具有较低的失调电压,大幅度提高了比较器的精度;较宽的输入共模电压范围及低功耗,可用于数字功放等高性能模拟IP模块的设计.     

几种用于高速数字通信系统中的锁存比较器

在分析、比较了高速数字系统中常用的几种低耗锁存比较器电路的基础上,重新提出了三种新颖的高速、低耗锁存比较器,其中有两种是BiCMOS锁存比较电路.经过仿真试验后,说明了这几种锁存比较器完全满足于高速数字通信系统的性能要求.     

一种分辨率为39μV的高精度比较器设计

该文主要介绍了一个应用于12bit SAR ADC中的高精度比较器。基于预放大锁存理论,完成了预放大级、锁存比较级和输出缓冲级三个模块的设计。为达到所需比较器的精度,对预放大级进行优化设计,锁存比较级电路采用的是动态锁存结构,而输出缓冲级采用的是SR锁存电路。该比较器是在GSMC 0.18μm工艺下完成仿真设计的,经测试,在300M时钟下,比较器的分辨率为39μV。     

用于威尔金森A/D转换器的高速高精度比较器

提出了一种用于威尔金森(Wilkinson) A/D转换器(ADC)的高速高精度比较器的设计方法.该比较器由三级预放大器和一级输出放大器组成,采用开环结构和多级级联的形式,以满足增益和速度的要求.为了消除失调电压对电路的影响,采用输出失调消除技术进行失调电压校正.采用3.3 V TSMC 0.18 μm CMOS工艺完成电路设计.Spectre仿真结果表明,在1 MHz最高采样频率下,该比较器的分辨率达到0.4 mV,传输延迟小于20 ns,满足12位Wilkinson ADC的要求.     

基于线性电流的锁存型灵敏放大器失调电压模型

随着CMOS技术的不断发展,由器件失配引起的失调电压对灵敏放大器的影响正逐渐地增大,在设计灵敏放大器前,如何准确地预测其失调电压已成为设计时的一个关键步骤。本文利用泰勒展开法,基于线性电流建立一种简单且精度较好的失调电压模型去评估锁存型灵敏放大器的输入失调电压。研究表明,模型的计算结果和Hspice的仿真结果能够很好吻合,它能够很好预测灵敏放大器的输入失调电压。     

一种高速高精度动态比较器

提出了一种应用于逐次逼近模数转换器的高速高精度比较器。该比较器由2级预放大器、1级锁存比较器以及缓冲电路构成。在前置预放大器中采用共源共栅结构、复位和箝位技术,提高了比较器的精度和速度,降低了功耗。在锁存比较器中引入额外的正反馈路径,提高了响应速度,降低了功耗。将锁存比较器输入对管与锁存结构隔离,降低了踢回噪声的影响,提高了比较器的精度。比较器基于SMIC 0.18 μm CMOS工艺进行设计与仿真。仿真结果表明,在1.8 V电源电压、800 MHz时钟下,比较器的精度为50 μV,传输延迟为458 ps,功耗为432 μW,芯片面积仅为0.009 mm²。     

An improved low offset latch comparator for high-speed ADCs

This paper presents a new high-speed and low offset latch comparator. The proposed offset compensation technique for latch comparator enables the preamplifier design relaxation for high-speed and high-resolution analog-to-digital converters. Employing the negative resistance of regeneration latch to enhance the comparator gain in input tracking phase is the key idea to reduce the latch input referred offset voltage. The Monte-Carlo simulation results for the designed comparator in 0.18 μm CMOS process show that equivalent input referred offset voltage is 200 μV at 1 sigma while it was 26 mV at 1 sigma before offset cancellation. The comparator dissipates 600 μW from a 1.8 V supply while operating in 500 MHz clock frequency.     

A 0.5 V offset cancelled latch comparator in standard 0.18 μm CMOS process

This paper presents a new 0.5 V high-speed dynamic latch comparator with built-in foreground offset cancellation capability and rail-to-rail input range. Traditional latch comparators lose their speed performance in low voltage condition, especially in sub-1V applications. The proposed latch comparator utilizes a speed-up technique based on a novel boosting method to mitigate the low voltage imperfections on circuit operation. Employing a new offset cancellation technique based on the same boosting capacitors is another key idea. This enhances the accuracy of the ultra low-voltage latch comparators and relaxes the need for preamplifier stage, which is conventionally used in the low offset latch comparator. The performed Monte Carlo simulations over corners in 0.18 μm standard CMOS process show the improvement of input referred offset voltage with a standard deviation of 29.9 mV/299 μV before and after offset cancellation, respectively. The designed comparator dissipates 34 μW power from 0.5 V voltage supply while operating in 200 MHz clock frequency and detects 1 mV input difference.     

一种中速高精度模拟电压比较器的设计

设计一种中速高精度模拟电压比较器,该比较器采用3级前置放大器加锁存器和数字触发电路的多级结构,应用失调校准技术消除失调,应用共源共栅结构抑制回程噪声干扰;应用数字触发电路获得高性能数字输出信号,设计采用0．35μm5VCMOS工艺实现一个输入电压2．5V、速度1MS／s、精度12位的逐次逼近型MD转换器。Hspice仿真结果表明：在5V供电电压下,速度可达20MHz,准确比较0．2mV电压,有效校准20mV输入失调,功耗约1mW。     

A novel low-offset dynamic comparator for sub-1-V pipeline ADCs

A novel low-offset dynamic comparator for high-speed low-voltage analog-to-digital converters (ADCs) has been proposed.In the proposed comparator,a CMOS switch takes the place of the dynamic current sources in the differential comparator,which allows the differential input transistors still to operate in the saturation region at the comparing time.This gives the proposed comparator a low offset as the differential comparator while tolerating a sub-1-V supply voltage.Additionally,it also features a larger input swing,less sensitivity to common mode voltage,and a simple relationship between the input and reference voltage.This proposed comparator with two traditional comparators has been realized by SMIC 0.13μm CMOS technology.The contrast experimental results verify these advantages over conventional comparators.It has been used in a 12-bit 100-MS/s pipeline ADC.     

A 100-MHz pipelined CMOS comparator

The authors describe the design of a VLSI-compatible CMOS comparator for high-speed applications. An examination of various generic approaches to obtaining the nonlinear amplification needed to perform the function of comparison leads to the conclusion that this amplification can best be obtained by means of regeneration. Based on this conclusion, a CMOS comparator has been designed wherein voltage comparisons are accomplished directly by a pipelined cascade of two regenerative sense amplifiers, without the use of a preamplifier. To ensure an input resolution of at least 8-bits, offset cancellation is incorporated in the first sense amplifier. The comparator has been integrated in a 2-μm CMOS technology and has a maximum sampling rate of over 100 MHz; it operates from a single +5-V supply and dissipates only 3.6 mW at its maximum sampling rate     

3.3-V BiCMOS current-mode logic circuits for high-speed adders

New high-speed BiCMOS current mode logic (BCML) circuits for fast carry propagation and generation are described. These circuits are suitable for reduced supply voltage of 3.3-V. A 32-b BiCMOS carry select adder (CSA) is designed using 0.5-μm BiCMOS technology. The BCML circuits are used for the correct carry path for high-speed operation while the rest of the adder is implemented in CMOS to achieve high density and low power dissipation. Simulation results show that the BiCMOS CSA outperforms emitter coupled logic (ECL) and CMOS adders     

多端I/O系统用BiCMOS连线逻辑电路

为了满足数字通信和信息处理系统多端输入/输出(I/O)、高速、低耗的性能要求,笔者设计了几例BiCMOS连线逻辑电路,并提出了采用0.5 mm BiCMOS工艺,制备所设计的连线逻辑电路的技术要点和元器件参数。所做实验表明了设计的连线逻辑电路既具有双极型逻辑门电路快速、大电流驱动能力的特点,又具备CMOS逻辑门低压、低功耗的长处,而且其扇入数可达3~16,扇出数可达1~18,因而它们特别适用于多端I/O高速数字通信和信息处理系统中。     

A high-speed latched comparator with low offset voltage and low dissipation

An ultra high-speed latched comparator using a controlled amount of positive feedback cell has been designed in TSMC 0.18 μm CMOS technique. Transmission gate (TG) switches are used to implement the preamplifier circuit. The use of TG switches results in a reduction in the power consumption of the high-speed comparator as well as clock feedthrough and the effect of charge injection. The simulation results demonstrate that it can work at 1.25 GHz suitable for high speed applications, and consumes 273.6 μW with a power supply of 1.8 V at 100 MHz and Monte Carlo simulation shows that the comparator has a low offset voltage approximately 0.499 mV.     

Evaluation of delay-time degradation of low-voltage BiCMOS based ona novel analytical delay-time modeling

The degradation of delay time of totem-pole BiCMOS, CBiCMOS, and BiNMOS circuits by supply voltage reduction is evaluated by a novel delay-time model. It has been found that base-collector capacitance plays a greater role in determining the delay time than other parasitic capacitances in BiCMOS circuits. It is concluded that when the input signal swings fully from zero to the supply voltage, the minimum supply voltage to guarantee high-speed operation over CMOS circuits is almost the same for the three kinds of BiCMOS circuits. When the input swing is reduced by the base-emitter voltage, however, BiNMOS and CBiCMOS circuits can operate on a lower supply voltage than totem-pole BiCMOS circuits     

红外焦平面读出电路集成数字输出

为了实现红外焦平面数字化输出,设计了一种集成片上模数转换的焦平面读出电路,包括一个512512的读出电路单元阵列和列共享的逐次逼近寄存器型模数转换器(SAR ADC)。单元读出电路采用了直接注入(DI)结构作为输入级,输出的信号通过多路传输送到模数转换器。设计的逐次逼近型的模数转换器中的比较器采用的是由前置放大器、锁存器、自偏置差分放大器和输出驱动器组成的高速比较器,数模转换器(DAC)采用的是三段式的电荷按比例缩放和电压按比例缩放相结合的结构。在Cadence和Synopsys设计平台下对模拟和数字部分电路分别进行设计、仿真与版图设计。电路工艺采用GLOBALFOUNDRIES公司0.35 m CMOS 3.3 V工艺加工流片。测试结果显示SAR ADC有效位数为8.2位,转换频率超过150 k Samples/s,功耗低于300 W,满足焦平面100帧频以及低功耗的需求。