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0.5μm部分耗尽SOI MOSFET的寄生双极效应严重影响了SOI器件和电路的抗单粒子和抗瞬态γ辐射能力。文中显示,影响0.5μm部分耗尽SOI NMOSFET寄生的双极器件特性的因素很多,包括NMOSFET的栅上电压、漏端电压和体接触等,尤其以体接触最为关键。在器件处于浮体状态时,0.5μm SOI NMOSFET的寄生双极器件很容易被触发,导致单管闭锁。因此,在设计抗辐射SOI电路时,需要尽量降低SOI NMOSFET寄生双极效应,以提高电路的抗单粒子和抗瞬态γ辐射能力。 相似文献
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SOI器件具有高速、低压、低功耗、抗辐照、耐高温等体硅器件不具备的优点,SOI CMOS技术开始用于深亚微米高速、低功耗、低电压大规模集成电路应用。但SOI技术还面临浮体效应、自加热效应等问题的挑战。作为SOI模型国际标准,BSIM3SOIv1.3提出了新的模型参数解决方案。BSIMPDSPICE器件模型是基于物理意义的模型,是在体硅MOS器件模型工业标准(BSIM3V3)的基础上开发而成,BSIMPD针对SOI固有的浮体效应引起的动态特性,自加热和体接触提出相应的模型参数。 相似文献
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It is important to understand what the floating-body effects are and how they affect device and circuit behavior. In this regard, this article qualitatively explains the device physics underlying DC and transient floating-body effects, clearly implying their influence on circuits, and thereby giving good insight into PD/SOI CMOS design issues. The article also notes special but practical device and circuit designs for controlling floating-body effects, showing through simulation how PD/SOI offers a significant performance advantage over bulk silicon in low-voltage applications, thereby conveying an assurance that reliable SOI CMOS design is feasible 相似文献
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Effect of floating-body charge on SOI MOSFET design 总被引:2,自引:0,他引:2
This work presents a new method for assessing the effect of floating-body charge on a fully- and partially-depleted Silicon-on-Insulator (SOI) MOSFET device design space. Floating-body effects under transient conditions are incorporated into the device design parameters threshold voltage VT and off-current I0FF using calibrated two-dimensional (2-D) device simulation. Simulation methodology which reveals the worst-case bounds of the device design parameters, from idle to switching-steady-state, is presented and applied to a CMOS inverter example. Using this methodology, the worst-case shifts in VT and I0FF due to hysteretic floating-body charge are quantified for devices in L eff=0.2- and 0.1-μm design spaces. Methods to reduce floating-body effects are discussed including a demonstration of how reducing the effective bulk carrier lifetime widens the 0.1-μm design space 相似文献
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A new model for the non-fully depleted (NFD) SOI MOSFET is developed and used to study floating-body effects in SOI CMOS circuits. The charge-based model is physical, yet compact and thus suitable for device/circuit simulation. Verified by numerical device simulations and test-device measurements, and implemented in (SOI)SPICE, it reliably predicts floating-body effects resulting from free-carrier charging in the NFD/SOI MOSFET, including the purportedly beneficial supra-ideal sub-threshold slope due to impact ionization and a saturation current enhancement due to thermal generation. SOISPICE CMOS circuit simulations reveal that the former effect is not beneficial and could be detrimental, but the latter effect can be beneficial, especially in low-voltage applications, when accompanied by a dynamic floating-body effect that effectively reduces static power. The dynamic floating-body effects are hysteretic, however, and hence exploitation of the beneficial ones will necessitate device/circuit design scrutiny aided by physical models such as the one presented herein 相似文献
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Workman G.O. Fossum J.G. Krishnan S. Pelella M.M. Jr. 《Electron Devices, IEEE Transactions on》1998,45(1):125-133
To simulate and examine temperature and self-heating effects in Silicon-On-Insulator (SOI) devices and circuits, a physical temperature-dependence model is implemented into the SOISPICE fully depleted (FD) and nonfully depleted (NFD) SOI MOSFET models. Due to the physical nature of the device models, the temperature-dependence modeling, which enables a device self-heating option as well, is straightforward and requires no new parameters. The modeling is verified by DC and transient measurements of scaled test devices, and in the process physical insight on floating-body effects in temperature is attained. The utility of the modeling is exemplified with a study of the temperature and self-heating effects in an SOI CMOS NAND ring oscillator. SOISPICE transient simulations of the circuit, with floating and tied bodies, reveal how speed and power depend on ambient temperature, and they predict no significant dynamic self-heating, irrespective of the ambient temperature 相似文献
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Shin H.C. Ik-Sung Lim Racanelli M. Wen-Ling Margaret Huang Foerstner J. Bor-Yuan Hwang 《Electron Devices, IEEE Transactions on》1996,43(2):318-325
Emphasis toward manufacturability of thin film SOI devices has prompted more attention on partially depleted devices. In this paper, drain current transients in partially depleted SOI devices due to floating-body effects are investigated quantitatively. A one-dimensional analytical model is developed to predict the transient effect and MEDICI simulation is performed to confirm the model. With the model, the amount of the turn-on current enhancement and the turn-off current suppression are calculated. The transient characteristics can be used in investigating the quality of the SOI materials by determining the carrier lifetime. The impact of the transient effect on the device parameter extraction is described 相似文献
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A simple model relating the hot-electron-controlled device lifetime of floating-body SOI MOSFETs to the body voltage is discussed. The model is derived from the familiar relationship between the device lifetime and the substrate current of bulk MOSFETs, a relationship that cannot be measured directly in floating-body MOSFETs. The model, which allows quick estimation of the device lifetime from body-voltage measurements, is supported by measurements of hot-electron-induced degradation of floating-body SOI MOSFETs fabricated using SIMOX substrates 相似文献
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Pelella M.M. Fossum J.G. Dongwook Suh Krishnan S. Jenkins K.A. Hargrove M.J. 《Electron Device Letters, IEEE》1996,17(5):196-198
An increased significance of the parasitic bipolar transistor (BJT) in scaled floating-body partially depleted SOI MOSFETs under transient conditions is described. The transient parasitic BJT effect is analyzed using both simulations and high-speed pulse measurements of pass transistors in a sub-0.25 μm SOI technology. The transient BJT current can be significant even at low drain-source voltages, well below the device breakdown voltage, and does not scale with technology. Our analysis shows that it can be problematic in digital circuit operation, possibly causing write disturbs in SRAMs and decreased retention times for DRAMs. Proper device/circuit design, suggested by our analysis, can however control the problems 相似文献
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The floating-body effect of nonvolatile memory cells fabricated using partially depleted silicon-on-insulator (SOI) technology has been investigated using two-dimensional numerical device simulation. Compared with similar bulk devices, the floating-body effect of partially depleted SOI MOSFETs introduces instability in the value of the drain current during sensing and extra hot-electron gate current in programming. The effects of the drain-current instability on the error margins in read operation are studied. The floating-body effect is found to be heavily dependent on biasing condition. 相似文献
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Pulse propagation problems associated with dynamic floating-body effects, e.g., pulse stretching, is measured in partially depleted SOI CMOS inverter chains. Pulse stretching is found to be dependent on pulse frequency and VDD. Such behavior is attributed to floating-body-induced transient threshold voltage variation in partially depleted SOI CMOS devices due to floating-body charge imbalance between logic states during CMOS switching. Such an imbalance can be minimized through proper device design because of the different dependencies of the gate and drain depletion charges on channel length, silicon film thickness, gate oxide thickness, channel doping, and supply voltage. This is confirmed by measuring the maximum transient threshold voltage variation in discrete partially depleted SOI NMOS devices in configurations which are predictive of CMOS switching behavior 相似文献
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Wen-Kuan Yeh Wen-Han Wang Yean-Kuen Fang Fu-Liang Yang 《Electron Device Letters, IEEE》2002,23(7):425-427
This letter investigates hot-carrier-induced degradation on 0.1 μm partially depleted silicon-on-insulator (SOI) nMOSFETs at various ambient temperatures. The thermal impact on device degradation was investigated with respect to body-contact nMOSFETs (BC-SOI) and floating-body SOI nMOSFETs (FB-SOI). Experimental results show that hot-carrier-induced degradation on drive capacity of FB-SOI devices exhibits inverse temperature dependence compared to that of BC-SOI devices. This is attributed to the floating-body effect (FBE) and parasitic bipolar transistor (PBT) effect 相似文献