一种高精度单环高阶Σ-Δ调制器

设计了一种高精度单环3阶Σ-Δ调制器。阐述了Σ-Δ调制器的结构,确定了前馈因子和增益因子等重要参数。对调制器的各种非理想因素,如时钟抖动、开关非线性、采样电容kT/C噪声等,进行了量化分析和行为级建模。采用MATLAB工具进行了系统验证。验证结果表明,调制器的采样频率为100 kHz,信噪比为99 dB,信噪比最大值为104.2 dB,有效精度达16 位。     

基于块数字滤波器的高阶两通道时间交织∑△调制器的系统优化设计

时间交织技术是一种提高∑△调制器采样频率的有效方法,但是时间交织∑△调制器对通道之间的失配非常敏感.在传统噪声传递函数(NTF)中增加一个z=-1的零点,可以减小折叠到信号带宽内的噪声.在已提出的基于块数字滤波器的二阶两通道时间交织∑△调制器结构的基础上,提出了一种高阶两通道时间交织∑△调制器的系统优化设计方法,该方法对系统的稳定性、噪声传递函数零极点的优化进行了考虑.采用该方法,设计了一种带宽为4MHz应用于数字视频广播系统中的高阶两通道时间交织调制器的系统结构.仿真结果表明,该调制器具有较大的稳定输入范围以及对通道失配不敏感的特点.     

一个过采增量—总和调制器的设计与实现

本文设计实现了一个高精度的双通道过采样Ａ／Ｄ电路，它采用由两个二阶调制器极联实现的四阶增量－总和调制器结构，并通过优化调制器内部各级增益，在改善过采样Ａ／Ｄ的人信号过载特性的同时提高其最大输出信噪比。为降低数字开关噪声对过采样Ａ／Ｄ性能的影响，本文采用了一种低噪声电流控制逻辑设计数字电路。实验芯片的测试结果表明，在６４倍的过采样率下，电流控制逻辑通道和静态ＣＭＯＳ逻辑通道分别获得了９１ｄＢ和８４．     

一种新型的相关焦平面CMOS读出电路

研究了一种新型相关双采样CTIA结构的焦平面读出电路，该电路采用光学调制器产生的信号来控制MOS管轮流导通，通过积分电容充放电，实现光电流转化为电压的过程。基于CSMC0．6μm DPDM CMOS工艺的BSIM 3V3 spice模型，采用Spectre对电路进行了仿真验证。在5V工作电源下，该读出方式在强背景应用中，不仅能有效地增加图像的动态范围和信噪比，而且也能提高输出电压摆幅、减小电路输出噪声。     

高精度低功耗Sigma-Delta调制器的设计

设计了一种应用于音频和传感领域的高精度低功耗的Sigma-Delta调制器。该调制器采用四阶单环一位的CRFF结构,通过开关电容型全差分电路的使用,减小了偶次谐波、衬底以及电源噪声,以及斩波技术的使用,降低了直流失调和低频噪声,达到了提高精度和降低功耗的目的。本设计采用Global foundries 0.18 μm CMOS工艺,电源电压为1.8 V,过采样率为128,采样时钟频率为5.12 MHz。仿真结果表明,该调制器信噪比达100.2 dB,整个调制器的功耗仅为380 μW。     

Delta Sigma调制器非理想因素建模

系统构建并研究了开关电容积分器DeltaSigma调制器非理想因素行为级模型.重点实现一种运放非线性直流增益模型,仿真表明它更有效反映奇次谐波失真,为保证模型真实性,综合考虑调制器其他非理想因素,如时钟抖动、量化器失配、采样噪声、开关非线性电阻以及运放参数(色化噪声、饱和电压、增益带宽、摆率等).     

功耗及信噪比双重约束下∑△模数调制器积分器优化

针对前馈级联∑△模数调制器结构,详细分析了调制器信噪比及功耗与Class-A类运算放大器构成的各级积分器等效输入噪声功率及功耗间相互关系,并在此基础上提出对于给定调制器信噪比及功耗双重约束的前馈级联∑△模数调制器各级积分器参数参考值的优化选取,包括:采样电容、开关导通电阻、输入晶体管宽长比等,从而有利于低功耗高精度∑△模数调制器设计者确定满足给定功耗和信噪比双重约束的∑△模数调制器优化设计方案,指导晶体管级电路设计,缩短设计周期.     

ADSL中宽带∑Δ调制器的系统设计

非对称数字用户环路(ADSL)是一种宽带接入网技术,对其调制解调器电路中模数转换器的带宽和精度要求较高。∑△调制器具有高精度和低功耗的优点,但是由于采用过采样技术,其带宽较小。为了增加带宽适合宽带应用,本文采用基于块数字滤波器的调制器结构设计了应用于ADSL的两通道二阶宽带∑△调制器系统。该∑△调制器在不提高系统时钟频率的条件下,可使系统的有效采样频率增为原来的两倍,从而使得其带宽增加1倍。采用带通噪声传递函数降低了由于通道系数失配而折叠到信号带宽内的噪声,提高了调制器的信号噪声失真比。利用SIMULINK软件工具对电路非理想特性进行了建模和仿真,仿真结果表明在系统时钟频率为71.4MHz,系数失配为0.5%的条件下,调制器的带宽为1.1MHz,噪声失真比为83.9dB,满足ADSL的应用要求,并且该调制器能够有效地抑制闲杂音,不需要采用随机扰动信号来抑制调制器的闲杂音,简化了后续的电路设计。     

标准数字工艺下16位精度低压低功耗ΣΔ模数调制器设计

针对输入信号频率在20 Hz～24 kHz范围的音频应用,该文采用标准数字工艺设计了一个1.2 V电源电压16位精度的低压低功耗ΣΔ模数调制器。在6 MHz采样频率下,该调制器信噪比为102.2 dB,整个电路功耗为2.46 mW。该调制器采用一种伪两级交互控制的双输入运算放大器构成各级积分器,在低电源电压情况下实现高摆率高增益要求的同时不会产生更多功耗。另外,采用高线性度、全互补MOS耗尽电容作为采样、积分电容使得整个电路可以采用标准数字工艺实现,从而提高电路的工艺兼容性、降低电路成本。与近期报道的低压低功耗ΣΔ模数调制器相比,该设计具有更高的品质因子FOM。     

微型加速计全差分Σ-Δ接口IC

主要描述一种加速度感应系统全差分Σ-ΔCMOS接口IC。电容传感器接口由一个前端可配置开关电容(SC)电荷放大器和一个末端,一阶SCΣ-Δ调制器组成。本设计采用开关双采样技术(CDS)来消减低频噪声,能有效地隔离高性能Σ-Δ调制器和MEMS传感器。采用0.35μm CMOS技术,在3.3 V电源环境下能够理想工作。仿真结果显示该设计能达到0.55 V/g的精度。     

一种10 MHz带宽70 dB动态范围连续时间Sigma-Delta调制器

介绍了4阶反馈型连续时间Sigma-Delta调制器从顶层到底层的详细设计过程。采用数字置乱技术,降低失配对输出杂散的影响,使失配产生的谐波被转换为噪声,并被移出通带外。将谐振腔内嵌于调制器环路中,以改善带内信噪比。采用三级前馈型放大器,调制器具备更高的能效。该调制器基于65 nm CMOS工艺设计并流片。测试结果表明,在时钟频率为614.4 MHz、信号带宽为10 MHz时,调制器的SNDR为70.1 dB,动态范围达70 dB。功耗为77 mW。该调制器芯片的内核面积为4.50 mm²。     

An I/Q mismatch-free switched-capacitor complex sigma-delta Modulator

This paper presents a technique to suppress the mismatch between the in-phase (I) and quadrature-phase (Q) channels of a switched-capacitor complex sigma-delta modulator that is used for the analog-to-digital conversion of a real intermediate-frequency radio signal. The mismatch is suppressed through time sharing of the critical capacitors, i.e., the input sampling capacitor and the capacitor of the feedback digital-to-analog converter, between the I and Q channels. Circuit simulations verifying the proposed technique are presented.     

Design of double-sampling /spl Sigma//spl Delta/ modulation A/D converters with bilinear integrators

Double-sampling techniques allow to double the sampling frequency of a switched capacitor /spl Sigma//spl Delta/ analog-to-digital convertors without increasing the clock frequency. Unfortunately, path mismatch between the double sampling branches may cause noise folding, which could ruin the modulator's performance. The fully floating double-sampling integrator is an interesting building block to be used in such a double sampling /spl Sigma//spl Delta/ modulator because its operation is tolerant to path mismatch. However, this circuit exhibits an undesired bilinear filter effect. This effectively increases the order of the modulator by one. Due to this, previously presented structures don't have enough freedom to fully control the modulator pole positions. In this paper, we introduce modified topologies for double-sampling /spl Sigma//spl Delta/ modulators built with bilinear integrators. We show that these architectures provide full control of the modulator pole positions and hence can be used to implement any noise transfer function. Additionally, analytical expressions are obtained for the residual folded noise.     

A second-order double-sampled delta-sigma modulator usingindividual-level averaging

A second-order double-sampled delta-sigma modulator is described. It uses all individual-level-averaging switching scheme to convert capacitor mismatch into high-pass noise. With a sampling rate of 25 MHz and an oversampling ratio of 128, the maximum measured signal-to-noise-and-distortion ratio is 82.2 dB, and the total harmonic distortion is -91.0 dB when the input is 2.5 dB below full scale. The modulator is fully differential, occupies 3.75 mm² in a 1.2-μm CMOS process, and dissipates 25.9 mW (10.2 mW analog and 15.7 mW digital)     

A 75-dB image rejection IF-input quadrature-sampling SC /spl Sigma//spl Delta/ Modulator

Quadrature sampling of intermediate frequency (IF) signals is subject to the well-known problem of gain and phase mismatches between the in-phase (I) and quadrature (Q) channels. This paper presents an IF-input quadrature-sampling switched-capacitor (SC) /spl Sigma//spl Delta/ modulator that circumvents the I/Q mismatch problem by time-sharing between the I and Q channels the critical circuit components, namely, the sampling capacitor and the capacitor of the first-stage feedback digital-to-analog converter (DAC). In addition, a clocking scheme that is insensitive to I/Q phase imbalance is used. A third-order single-loop 1-bit low-pass modulator has been designed and fabricated in a 0.35-/spl mu/m CMOS process with an active area of 0.57mm/sup 2/. The experimental results show that the modulator achieves an image-rejection ratio (IRR) of greater than 75dB throughout a 200-kHz signal bandwidth.     

Cascaded Complex ADCs With Adaptive Digital Calibration for $I/Q$ Mismatch

A complex analog-to-digital converter (ADC) intended for digital intermediate frequency (IF) receiver applications digitizes analog signals at IFs with excellent power/bandwidth efficiency. However, it is vulnerable to mismatches between its in-phase and quadrature (I/Q) paths that can dramatically degrade its performance. The proposed solution mitigates I/Q mismatch effects using a complex sigma-delta (SigmaDelta) modulator cascaded with 9-bit pipeline converters in each of the I and Q paths. The quantization noise of the first stage complex modulator is eliminated using an adaptive scheme to calibrate finite-impulse response digital filters in the digital noise-cancellation logic block. Although low-pass SigmaDelta cascade ADCs are widely used because of their inherent stability and high-order noise shaping, the complex bandpass cascade architecture introduced herein maintains these advantages and doubles the noise shaping bandwidth. Digital calibration also reduces the effects of analog circuit limitations such as finite operational amplifier gain, which enables high performance and low power consumption with high-speed deep-submicrometer CMOS technology. Behavioral simulations of the complex SigmaDelta/pipeline cascade bandpass ADC using the adaptive digital calibration algorithm predict a signal-to-noise ratio (SNR) of 78 dB over a 20-MHz signal bandwidth at a sampling rate of 160 MHz in the presence of a 1% I/Q mismatch.     

A CMOS oversampling bandpass cascaded D/A converter with digital FIR and current-mode semi-digital filtering

An oversampling bandpass digital-to-analog converter has been designed so as to eliminate the carrier leak and in-band SNR degradation that accompany I and Q channel mismatch in wireless transmitters. The converter combines a cascaded noise-shaping sigma-delta (/spl Sigma//spl Delta/) modulator with digital finite impulse response (FIR) and mixed-signal semi-digital filters that attenuate out-of-band quantization noise. The performance of the converter in the presence of current source mismatch has been improved through the use of bandpass data weighted averaging. An experimental prototype of the converter, integrated in a 0.25-/spl mu/m CMOS technology, provides 83 dB of dynamic range for a 6.25-MHz signal band centered at 50 MHz, and suppresses out-of-band quantization noise by 38 dB.