一个面向缺陷分析的电路成品率与可靠性的关系模型

在电路设计的早期阶段,成品率与可靠性的关系模型对于预测和改善电路的成品率和可靠性具有极为重要的意义.结合广义门电路的版图结构与拓扑结构信息,分析了其缺陷密度及成品率和可靠性的损失机理,并构建了考虑缺陷生长特性的广义门电路成品率与可靠性损失概率之间的解析关系模型.基于该模型,又考虑到电路拓扑结构对故障的屏蔽效应,利用迭代的概率转移矩阵方法给出了门级电路成品率与可靠性之间的量化关系.理论分析与通过在ISCAS85基准电路上采用经验公式和惯用方法的证明策略,验证了本文所提方法的合理性和有效性.还分析了工艺参数、老化因素等对电路成品率与可靠性关系的影响.     

基于缺陷均匀分布的集成电路制造成品率与可靠性之间的关系模型

在集成电路可制造性设计研究中,成品率与可靠性之间的关系模型备受人们关注.缺陷对成品率和可靠性的影响不仅与出现在芯片上的缺陷粒径大小有关而且与缺陷出现在芯片上的位置有关.本文主要考虑了出现在互连线上的金属丢失物缺陷对互连线的影响,分析了同一粒径的缺陷出现在互连线不同位置对互连线有效宽度的影响,给出了基于缺陷均匀分布的互连线平均有效宽度,结合已有成品率和可靠性估计模型,提出了基于缺陷位置信息的集成电路制造成品率与可靠性之间的关系模型.在工艺线稳定的情况下,利用该工艺线的制造成品率可以通过该关系式有效地估计出产品的可靠性,从而有效地缩短新产品的研发周期.     

基于离散模型的IC可靠性与成品率关系

集成电路的可靠性和成品率是制约半导体制造发展的两个主要因素.如何表征可靠性和成品率之间的关系是一个非常重要的问题.本文利用一种离散的成品率模型导出了二者的关系式,该关系式不仅考虑了线宽、线间距等版图的几何信息同时还考虑了与工艺有关的缺陷粒径分布等参数.通过模拟实验给出了该模型的有效性验证.     

基于工艺参数扰动的IC参数成品率多目标优化算法

在芯片制造工艺中,参数扰动影响了集成电路（Integrated Circuit,IC）成品率,使不同参数成品率间存在着此消彼长的相互制约关系,而目前IC参数成品率优化算法却主要局限于单一优化目标问题。本文提出一种基于工艺参数扰动的参数成品率多目标优化算法。该算法针对漏电功耗成品率及芯片时延成品率,首先构建具有随机相关性的漏电功耗及芯片时延统计模型;随后根据其相互制约特性建立基于切比雪夫仿射理论的参数成品率多目标优化模型;最后利用自适应加权求和得到分布均匀的帕雷托优化解。实验结果表明,该算法对于具有不同测试单元的实验电路均可求得大约30个分布均匀的帕雷托优化解,不仅能够有效权衡多个优化目标间的相互制约关系,还可以使传统加权求和优化方法在帕雷托曲线变化率较小之处得到优化解。     

考虑缺陷形状分布的IC成品率模型

实现了基于圆缺陷模型的蒙特卡洛关键面积及成品率估计,模拟了圆缺陷模型估计的成品率误差与缺陷的矩形度之间的关系,提出了更具有一般性的两种集成电路成品率模型,它们分别对应于矩形度相同和不同的缺陷．仿真结果表明该模型为成品率的精确表征提供了新途径．     

基于IC互连线开路故障的Y/R模型

在半导体制造业中,IC的成品率和可靠性(Y/R)是倍受关注的两个问题.研究表明它们之间存在着显著的相关性.为了表征这种相关性,本文从缺陷造成互连线开路的机理出发,分析了成品率关键面积和可靠性关键面积,提出了IC成品率与可靠性关系模型.通过模拟实验给出了该模型的有效性验证.     

半导体器件成品率与可靠性之间的关系研究

对国外近几年在半导体器件成品率与可靠性之间的关系研究情况进行了综合、分析 ,介绍了成品率预计模型及其参数的选取。     

基于制造成品率模型的集成电路早期可靠性估计

缺陷是影响集成电路成品率与可靠性的主要因素.本文在区分缺陷与故障两个概念的基础上,将缺陷区分为成品率缺陷(硬故障)、可靠性缺陷(软故障)和良性缺陷.利用关键区域的面积,给出了一个缺陷成为"硬故障"或"软故障"的概率,给出了精度较高的IC成品率预测模型.利用成品率缺陷与可靠性缺陷之间的关系,给出了工艺线生产的产品的失效率与该工艺线制造成品率之间的定量关系.在工艺线稳定的条件下,通过该工艺线的制造成品率可以利用该关系式可以有效的估计出产品的失效率,可以有效地缩短了新产品的研发周期.     

半导体器件成品率的高低是产品质量与可靠性高低的"预示"

介绍了国外半导体器件成品率与可靠性之间关系的研究结果，提出了元器件成品率的高低，是产品质量与可靠性高低的“预示”这一观点。同时还对成品率损失的原因、影响产品质量和可靠性的原因进行了分析，为内建可靠性、提高产品的成品率、质量和可靠性提供参考。     

考虑缺陷形状分布的IC成品率模型

实现了基于圆缺陷模型的蒙特矩形度之间的关系,提出了更具有一般性的两种集成电路成品率模型,它们分别对应于矩形度相同和不同的缺陷.仿真结果表明该模型为成品率的精确表征提供了新途径.     

Relation between yield and reliability of integrated circuits and application to failure rate assessment and reduction in the one digit FIT and PPM reliability ERA

Clear relations have been established between E-sort yield and burn-in, EFR and field failure rates for nearly 50 million high volume products in bipolar, CMOS and BICMOS technologies from different waferfabs. The correlations obey a simple model that assumes that the reliability defect density is a fraction of the waferfab defect density and that rootcauses of failures are the same. The model allows a die size independent prediction and assessment of FIT and PPM reliability levels of an IC just based on its yield, eliminating the need for excessive lifetesting. ‘Maverick’ batches are identified by more than 2 to 3 rejects per batch and can not be eliminated by scrap of low yielding wafers alone. For non-mature technologies only correlations with functional yield are found, the parametric yield loss can be disregarded. Using the results, it is shown how reliability can be improved in a fast and controlled way, even in the 1 digit FIT and PPM reliability era, by reducing waferfab defect density, elimination of special causes and implementation of screens at product test like voltage screen and Iddq testing. As the effect of yield on PPM reject level is not that strong, the latter approach can be very effective in improving reliability.     

Reliability functions estimated from commonly used yield models

Reliability can be estimated from a semiconductor yield model once in-process measurements of manufacturing defects are obtained which cause both yield and reliability losses. Such reliability is more useful, than reliability estimated from field failure data, for determining during the early production stage whether a reliability requirement will be met or not. The purpose of this paper is to investigate and compare reliability functions estimated from previous yield models that are commonly used in literature. The results characterize the impact of defect clustering and environmental conditions on reliability estimated from yield.     

集成电路可制造性工程与设计方法学

集成电路可制造性工怀设计是近年来发展很快的研究领域，它集ＩＣ设计、制造、封装和测试过程为一体，在统一框图（即产品制造成本和成品率驱动下）下，对产品进行规划和设计，应用该设计可以大大缩短ＩＣ产品研制周期，降低制造成本，提高成品率和可靠性，本文将综述该领域的研究进展，并阐述进一步的研究方向。     

Investigations on the Susceptibility of ICs to Power-Switching Transients

Due to the fast changes of the voltage and current generated by the operation of power-switching circuits that supply inductive loads, wideband transients can be induced at the ports of electronic equipment operating in the same environment. The level of collected transients is responsible for the degradation of system performance as well as its reliability. This paper describes a circuit model by which the transient waveforms at the equipment ports can be analyzed for real applications in the early design stages. A compact injection probe, whose properties derive from simulations performed on the circuit model and on the results of experimental measurements, has been designed and fabricated to characterize IC susceptibility to electrical transients.      

基于试验设计技术的IC可靠性优化设计

现代IC设计对设计者提出了更多要求,不仅要求电路满足特定功能,而且还需要满足高质量和可靠性的要求.集成电路可靠性设计的目标是使性能对不可控因素不敏感,仅依靠EDA仿真很难完成这类设计.本文探讨了利用响应曲面(RSM)统计试验设计(DOE)与电路仿真相结合对集成电路进行可靠性优化设计的方法.并将该方法应用于电压带隙基准电路可靠性优化设计.优化确定的参数组合在满足电路指标同时,对温度的变化更加不敏感,提高了电路的可靠性要求.     

VLSI容错设计研究进展(2)——功能成品率与可靠性的研究

带冗余的集成电路的成品率的估计对制造者来说是一个非常重要的问题。文中将集中分析和讨论带冗余的成品率模型和可靠性,给出了该领域研究进展的最新结果,并指出了进一步研究的方向和策略。     

Interconnect Lifetime Prediction for Reliability-Aware Systems

Thermal effects are becoming a limiting factor in high-performance circuit design due to the strong temperature dependence of leakage power, circuit performance, IC package cost, and reliability. While many interconnect reliability models assume a constant temperature, this paper analyzes the effects of temporal and spatial thermal gradients on interconnect lifetime in terms of electromigration, and presents a physics-based dynamic reliability model which returns reliability equivalent temperature and current density that can be used in traditional reliability analysis tools. The model is verified with numerical simulations and reveals that blindly using the maximum temperature leads to too pessimistic lifetime estimation. Therefore, the proposed model not only increases the accuracy of reliability estimates, but also enables designers to reclaim design margin in reliability-aware design. In addition, the model is useful for improving the performance of temperature-aware runtime management by modeling system lifetime as a resource to be consumed at a stress-dependent rate     

基于IC产品分档的成品率与效益协调优化设计方法

文章在对IC产品按性能优劣分档的基础上，构造了一个既能体现IC产品的性能优劣和价格大小，又可根据各档次IC产品的市场价格进行调节的性能价格函数：Ep(X)=-1pln{e^-p ∑Mi=1e^P(kiΦi(x)-α)}，从而建立了成品率与效益协调优化模型：maxX^0YE(X^0)=∫R^aEp(X)P(X,X^0)dX。