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CMOS射频集成电路ESD保护的挑战
引用本文:王自惠,林琳,王昕,刘海南,周玉梅.CMOS射频集成电路ESD保护的挑战[J].半导体学报,2008,29(4):628-636.
作者姓名:王自惠  林琳  王昕  刘海南  周玉梅
作者单位:[1]Department of Electrical Engineering, University of California, Riverside, CA 92521, USA [2]中国科学院微电子研究所,中国北京100029
基金项目:国家自然科学基金 , Citrus Com Semiconductor资助项目
摘    要:随着集成电路(IC)T艺进入深亚微米水平,以及射频(Radi0.Frequency,RF)IC工作频率向数千兆赫兹频段迈进,片上防静电泄放(ESD)保护设计越来越成为RF IC设计的挑战.产生这一挑战的关键原因在于ESD保护电路和被保护的RF IC核电路之间存在着不可避免的复杂交互影响效应.本文讨论了RF ESD保护的研究和设计领域的最新动态,总结了所出现的新挑战、新的设计方法和最新的RF ESD保护解决方案.

关 键 词:静电泄放  ESD保护  射频ESD  寄生效应  electrostatic  discharge  ESD  protection  RF  ESD  parasitic
文章编号:0253-4177(2008)04-0628-09
修稿时间:12/4/2007 8:56:35 AM

Emerging Challenges in ESD Protection for RF ICs in CMOS
Wang Albert,Lin Lin,Wang Xin,Liu Hainan and Zhou Yumei.Emerging Challenges in ESD Protection for RF ICs in CMOS[J].Chinese Journal of Semiconductors,2008,29(4):628-636.
Authors:Wang Albert  Lin Lin  Wang Xin  Liu Hainan and Zhou Yumei
Affiliation:Department of Electrical Engineering,University of California,Riverside,CA 92521,USA;Department of Electrical Engineering,University of California,Riverside,CA 92521,USA;Department of Electrical Engineering,University of California,Riverside,CA 92521,USA;Institute of Microelectronics, Chinese Academy of Sciences,Beijing 100029,China;Institute of Microelectronics, Chinese Academy of Sciences,Beijing 100029,China
Abstract:On-chip electrostatic discharge (ESD) protection design has become an emerging challenge for radio-frequency (RF) integrated circuits (IC) design as IC technologies migrate into the very-deep-sub-micron (VDSM) regime and RF ICs move into multi-GHz operations.The key problem originates from the complex interaction between the ESD protection circuitry and the core RF IC circuit under protection.This paper discusses the recent development in RF ESD protection research and design,outlining emerging challenges,new design methods,and novel RF ESD protection solutions.
Keywords:electrostatic discharge  ESD protection  RF ESD  parasitic
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