Fabrication and optical-switching results of the double-gate static-induction thyristor with the first planar-gate and the second buried-gate structure

A new thyristor structure-a class of the double-gate (DG) static-induction (SI) thyristors-was fabricated and showed quick dual-gate current controllability and less turn-off tailing current, because the anode current can be controlled by both the first and the second gate and the electrons stored at the second gate can be discharged through the second gate circuit in a very short time at the turn-off process. Moreover, the DG SI thyristors have a capability of lower forward voltage drop and faster switching speed than those values of the single-gate SI thyristor.     

Vertical channel field-controlled thyristors with high gain and fast switching speeds

A new, planar, surface-grid, field-controlled thyristor (FCT) structure is described. The structure is fabricated by using orientation-dependent (preferential) etching and selective vapor epitaxial growth to obtain vertical grid walls. The resulting high channel-length-to-width aspect ratio produces devices with high blocking gains and fast gate turnoff speeds. Devices have been fabricated with the capability of blocking more than 1000 V with an applied grid bias of 32 V, and simultaneously exhibiting a low forward voltage drop in the on-state. These surface-grid devices exhibit gate turnoff capability with turnoff times of less than 500 ns at a rated cathode-anode current of 1 A.     

The asymmetrical field-controlled thyristor

A new device structure has been developed for field-controlled thyristors. In this structure, the uniformly doped n base of the conventional device has been replaced with a very lightly doped region near the gate and a more heavily doped region at the anode. This change in the base doping profile results in a significant improvement in the tradeoff between the forward-blocking voltage capability and the on-state forward-voltage drop. In addition, the high-resistivity region around the gate area allows the device to pinch off anode current flow at zero gate bias due to the built-in potential of the gate junction. The devices can, however, be triggered to the on-state by applying a small forward gate voltage and exhibit a forward voltage drop in the on-state which is much lower than that of conventional devices. The high resistivity of the channel area between gates also results in these devices having dc blocking gains in excess of 60, which is the highest value achieved in devices of this type. Further, because these devices have been fabricated using conventional planar processing techniques, this structure is suitable for high-volume production with high processing yields.     

High current density 800-V 4H-SiC gate turn-off thyristors

4H-SiC gate turn-off thyristors (GTOs) were fabricated using the recently developed inductively-coupled plasma (ICP) dry etching technique. DC and ac characterisation have been done to evaluate forward blocking voltage, leakage current, on-state voltage drop and switching performance. GTOs over 800 V dc blocking capability has been demonstrated with a blocking layer thickness of 7 μm. The dc on-state voltage drops of a typical device at 25 and 300°C were 4.5 and 3.6 V, respectively, for a current density of 1000 A/cm². The devices can be reliably turned on and turned off under an anode current density of 5000 A/cm² without observable degradation     

A 2.5-kV static induction thyristor having new gate and shorted p-emitter structures

An SI thyristor with new gate and shorted p-emitter structures (DTT-SI thyristor) is proposed to realize a high-voltage high current high-speed device having a low forward voltage drop. Investigations using fabricated 2.5-kV 100-A DTT-SI thyristors and numerical analyses show that the DTT-SI thyristor has a good trade-off between the forward voltage drop and switching characteristics when the channel width is 8-10 µm and the maximum impurity concentration is about 1 × 10¹⁷to 4 × 10¹⁷cm^-3. The typical fabricated DTT-SI thyristor has a 2.5-kV forward blocking voltage with a 58-V reverse gate bias voltage, a 1.4-V forward voltage drop with a 100-A anode current, a 2- µs turn-on time, adi/dtcapability higher than 4000 A/µs, and can interrupt a 900-A anode current with a 3.5-µs turn-off time and a 5.6 gate turn-off gain on application of a 100-V reverse gate bias voltage.     

Fabrication of self-aligned graded junction termination extensions with applications to 4H-SiC P-N diodes

The properties of SiC make this wide band-gap semiconductor a promising material for high power devices. This potential is demonstrated in various devices, such as p-n diodes, Schottky diodes, bipolar junction transistors, thyristors, etc., all of which require adequate and affordable termination techniques to reduce leakage current and increase breakdown voltage in order to maximize power-handling capabilities. In this paper, we describe a technique for fabricating a graded junction termination extension (GJTE) that is effective and self-aligned, a feature that simplifies the implantation process during fabrication and, therefore, has the potential to reduce production costs. Implanted anode p-n diodes fabricated using this technique on 10-μm thick n⁻ epitaxial layer had a maximum breakdown voltage of 1830 V. This was comparable to the ideal parallel-plane breakdown of 1900 V predicted by numerical simulation.     

Effect of p-base sheet and contact resistances on staticcurrent-voltage characteristics of scaled low-voltage vertical powerDMOSFETs

Static current-voltage characteristics of low-voltage scaled power double-diffused MOSFETs fabricated using selectively formed TiSi₂ films on gate polysilicon and source contact regions are reported. It is shown that considerable modulation of drain-source current-voltage characteristics results from increased p-base sheet and contact resistances. This effect is found to vanish at higher operating temperatures. Increased p-base contact resistance also results in a large forward voltage drop for the body p-n junction diode     

Low-loss high-speed switching devices, 2300-V 150-A static induction thyristor

Focussing attention to the performance of high-speed high off-state voltage and large current provided in the buried-gate-type static induction (SI) thyristor, a 2300-V 150-A low-voltage-drop high-speed medium-power SI thyristor was developed. Irrespective of the magnitude of switching current, the SI thyristor has the characteristics of fast turn-on time and less on-gate current compared to that of the GTO thyristor. The characteristics of this SI thyristor obtained as the result of manufacturing this prototype were such that the forward blocking voltage was 2300 V at a gate reverse voltage of -5 V, the reverse blocking voltage was 2350 V, and the forward voltage drop was 1.4 V at an anode current of 150 A and 2.2 V at an anode current of 450 A. The switching characteristics were such that the turn-on time was 1.5 µs when an anode current IAof 150 A becomes ON, turnoff time was 2.5 µs at IA= 100 A and 3.6 µs at IA= 200 A. This SI thyristor is able to break the anode current of 1000 A at a gate current of 95 A. Performance exceeding 1100 A/µs was confirmed for the di/dt capability and even for dv/dt, and these normally can be operatable even at 100 times higher current compared with maximum average current.     

Monolithically integrated enhancement/depletion-mode AIGaN/GaN HEMT D flip-flop using fluorine plasma treatment

Depletion-mode and enhancement-mode AlGaN/GaN HEMTs using fluorine plasma treatment were integrated on one wafer. Direct-coupled FET logic circuits, such as an E/D HEMT inverter, NAND gate and D flip-flop, were fabricated on an AlGaN/GaN heterostructure. The D flip-flop and NAND gate are demonstrated in a GaN system for the first time. The dual-gate AlGaN/GaN E-HEMT substitutes two single-gate E-HEMTs for simplifying the NAND gate and shrinking the area, integrating with a conventional AlGaN/GaN D-HEMT and demonstrating a NAND gate. E/D-mode D flip-flop was fabricated by integrating the inverters and the NAND gate on the AlGaN/GaN heterostructure. At a supply voltage of 2 V, the E/D inverter shows an output logic swing of 1.7 V, a logic-low noise margin of 0.49 V and a logic-high noise margin of 0.83 V. The NAND gate and D flip-flop showed correct logic function demonstrating promising potential for GaN-based digital ICs.     

F等离子体处理增强型及耗尽型AlGaN/GaN HEMT集成的D触发器

耗尽型和F等离子体处理增强型高电子迁移率晶体管（HEMT）被集成在同一圆片上。增强型/耗尽型 HEMT反向器、与非门以及D触发器等直接耦合场效应晶体管逻辑电路被制作在AlGaN/GaN异质结上。D触发器在GaN体系中首次被实现。在电源电压为2伏的条件下,增强型/耗尽型反向器显示输出逻辑摆幅为1.7伏,逻辑低噪声容限为0.49伏,逻辑高噪声容限为0.83伏。与非门和D触发器的功能正确,证实了GaN基数字电路的发展潜力。     

High-voltage high-power gate-assisted turn-off thyristor for high-frequency use

The fast switching thyristor with an integrated rectifier-diode connected in antiparallel to the cathode-emitter junction of auxiliary thyristor has been made. This thyristor has the ratings of blocking voltage 1200 V, average current 400 A. The turn-off time of less than 6 µs can be obtained by applying -10 V gate bias. It has the interdigitated gate structure and the high-frequency current rating more than 500 A at 10 kHz.     

2700V4H-SiC结势垒肖特基二极管

在76.2 mm 4H-SiC晶圆上采用厚外延技术和器件制作工艺研制的结势垒肖特基二极管(JBS).在室温下,器件反向耐压达到2700 V.正向开启电压为0.8V,在VF=2V时正向电流密度122 A/cm2,比导通电阻Ron=8.8 mΩ·cm2.得到肖特基接触势垒qφв=1.24 eV,理想因子n=1.     

A power junction gate field-effect transistor structure with high blocking gain

A new gate structure is described for vertical-channel power junction gate field-effect transistors (FET's). This gate structure has vertically walled gate regions extending perpendicular to the wafer surface. The structure is fabricated by using orientation-dependent silicon etching and selective vapor-phase epitaxial refill techniques. In comparison to previous gate structures made by planar diffusion, the vertically walled gate structure exhibits one order of magnitude improvement in blocking gain. This improvement in blocking gain has allowed the fabrication of devices having breakdown voltages above 400 V and a current-handling capability of more than 0.5 A with an on-resistance of 12 Ω. The devices are designed to exhibit pentode-like characteristics at low gate voltages and triode-like characteristics at large reverse gate bias voltages in order to obtain the observed high-power handling capability.     

1200V大容量SiC MOSFET器件研制

采用平面栅MOSFET器件结构,结合优化终端场限环设计、栅极bus-bar设计、JFET注入设计以及栅氧工艺技术,基于自主碳化硅工艺加工平台,研制了1200V大容量SiC MOSFET器件.测试结果表明,器件栅极击穿电压大于55V,并且实现了较低的栅氧界面态密度.室温下,器件阈值电压为2.7V,单芯片电流输出能力达到50A,器件最大击穿电压达到1600V.在175℃下,器件阈值电压漂移量小于0.8V;栅极偏置20V下,泄漏电流小于45nA.研制器件显示出优良的电学特性,具备高温大电流SiC芯片领域的应用潜力.     

A low-power high-speed ion-implanted JFET for InP-based monolithic optoelectronic IC's

We describe a high-performance fully ion-implanted planar InP junction FET fabricated by a shallow (4000-Å) n-channel implant, an n⁺source-drain implant to reduce FET series resistance, and a p-gate implant to form a shallow (2000-Å) abrupt p-n junction, followed by a rapid thermal activation. From FET's with gates 2 µm long, a transconductance of 50 mS/mm and an output impedance of 400 Ω.mm are measured at zero gate bias with a gate capacitance of 1.2 pF/mm. The FET has a threshold voltage of -2.4 V, and a saturated drain current of 60 mA/mm at Vgs= 0 V with negligible drift.     

GaN/AlGaN p-channel inverted heterostructure JFET

A novel GaN/AlGaN p-channel inverted heterostructure junction field-effect transistor (HJFET) with a n/sup +/-type gate is proposed and demonstrated. A new superlattice aided strain compensation techniques was used for fabricating high quality GaN/AlGaN p-n junction. The p-channel HJFET gate leakage current was below 10 nA, and the threshold voltage was 8 V, which is close to that of typical n-channel HFETs. This new HJFET device opens up a way for fabricating nitride based complimentary integrated circuits.     

L波段0.5mm SiC SIT

作为测试小管芯,所研制的小栅宽(0.5 mm)L波段SiC SIT器件,台面和栅凹槽线宽分别为1.0 μm和1.5 μm,源间距2.5 μm,采用凹栅结构、Al注入形成PN结等优化手段,提高了器件的击穿特性和微波特性.0.5 mm栅宽SiC SIT器件,输出功率通过负载牵引系统进行测试,在1.2 GHz CW、50 V...     

A high gain n-well/gate tied PMOSFET image sensor fabricated from astandard CMOS process

The performance of a high gain photodetector fabricated using a standard 0.8-μm, triple metal, n-well CMOS process is reported, The photodetector is formed by connecting the gate of the PMOSFET and n-well together while keeping both floating. The depletion region induced by the floating gate and the well-to-substrate p-n junction separate the optically generated electron-hole pairs in the direction perpendicular to the current flow. The n-well potential modulated by illumination is fed back to the gate through the well-to-gate connection, which results in an extra current amplification beyond that of a normal PMOSFET biased in the lateral bipolar mode. A high responsivity of 2.5×10³ A/W has been measured with an operating voltage as low as 0.3 V for a W/L of 8.2 μm/0.8 μm. The impact of technology scaling on the performance of the photodetector are also studied. A simple 32×32-pixel image sensor array was fabricated to demonstrate the feasibility of integrating the new device in actual circuit applications     

An 1800 V triple implanted vertical 6H-SiC MOSFET

6H silicon carbide vertical power MOSFETs with a blocking voltage of 1800 V have been fabricated. Applying a novel processing scheme, n ⁺ source regions, p-base regions and p-wells have been fabricated by three different ion implantation steps. Our SiC triple ion implanted MOSFETs have a lateral channel and a planar polysilicon gate electrode. The 1800 V blocking voltage of the devices is due to the avalanche breakdown of the reverse diode. The reverse current density is well below 200 μA/cm² for drain source voltages up to 90% of the breakdown voltage. The MOSFETs are normally off showing a threshold voltage of 2.7 V. The active area of 0.48 mm² delivers a forward drain current of 0.3 A at Y_GS=10 V and V _DS=8 V. The specific on resistance was determined to 82 mΩdcm² at 50 mV drain source voltage and at V_GS =10 V which corresponds to an uppermost acceptable oxide field strength of about 2.7 MV/cm. This specific on resistance is an order of magnitude lower than silicon DMOSFET's of the same blocking capability could offer     

A novel fabrication process of a silicon field emitter array withthermal oxide as a gate insulator

We have successfully developed a fabrication process of a silicon field emitter array with a gate insulator formed by Si₃N₄ sidewall formation and subsequent thermal oxidation. This process overcomes some problems in the conventional fabrication, such as high etch rate, low breakdown field, and gate hole expansion arising from evaporation of gate oxide. Therefore, we could improve process stability and emission performance, and also reduce gate leakage current. The optimum process conditions were determined by process simulations using SUPREM-4. The turn-on voltage of the fabricated field emitters was approximately 38 V. An anode current of 0.1 μA (1 μA) per tip was measured for a 625-tip array at the gate bias of 80 V (100 V), and the gate current was less than 0.3% of the anode current at those emission levels