适用于中频采样的低功耗时间交织10位250Msps电荷域流水线ADC

A 10-bit 250-MSPS two-channel time-interleaved charge-domain(CD) pipelined analog-to-digital converter (ADC) is presented.MOS bucket-brigade device(BBD) based CD pipelined architecture is used to achieve low power consumption.An all digital low power DLL is used to alleviate the timing mismatches and to reduce the aperture jitter.A new bootstrapped MOS switch is designed in the sample and hold circuit to enhance the IF sampling capability.The ADC achieves a spurious free dynamic range(SFDR) of 67.1 dB,signal-to-noise ratio (SNDR) of 55.1 dB for a 10.1 MHz input,and SFDR of 61.6 dB,SNDR of 52.6 dB for a 355 MHz input at full sampling rate.Differential nonlinearity(DNL) is +0.5/-0.4 LSB and integral nonlineariry(INL) is +0.8/-0.75 LSB.Fabricated in a 0.18-μm 1P6M CMOS process,the prototype 10-bit pipelined ADC occupies 1.8×1.3 mm2 of active die area,and consumes only 68 mW at 1.8 V supply.     

用于流水线ADC的频率自适应可编程MDAC电路

A programmable high precision multiplying DAC （MDAC） is proposed. The MDAC incorporates a frequency-current converter （FCC） to adjust the power versus sampling rate and a programmable operational am- plifier （POTA） to achieve the tradeoff between resolution and power of the MDAC, which makes the MDAC suitable for a 12 bit SHA-less pipelined ADC. The prototype of the proposed pipelined ADC is implemented in an SMIC CMOS 0.18 μm 1P6M process. Experimental results demonstrate that power of the proposed ADC varies from 15.4 mW （10 MHz） to 63 mW （100 MHz） while maintaining an SNDR of 60.5 to 63 dB at all sampling rates. The differential nonlinearity and integral nonlinearity without any calibration are no more than 2.2/-1 LSB and 1.6/-1.9 LSB, respectively.     

一种带有混合平均式分布采样电路的低功耗CMOS全折叠型模数转换器

This paper describes an 8-bit 125 MHz low-power CMOS fully-folding analog-to-digital converter （ADC） A novel mixed-averaging distributed T/H circuit is proposed to improve the accuracy. Folding circuits are not only used in the fine converter but also in the coarse one and in the bit synchronization block to reduce the number of comparators for low power. This ADC is implemented in 0.5μm CMOS technology and occupies a die area of 2 × 1.5 mm^2. The measured differential nonlinearity and integral nonlinearity are 0.6 LSB/-0.8 LSB and 0.9 LSB/-1.2 LSB, respectively. The ADC exhibits 44.3 dB of signal-to-noise plus distortion ratio and 53.5 dB of spurious-free dynamic range for 1 MHz input sine-wave. The power dissipation is 138 mW at a sampling rate of 125 MHz at a 5 V supply.     

On the design of high-speed energy-efficient successive-approximation logic for asynchronous SAR ADCs

This paper analyzes the power consumption and delay mechanisms of the successive-approximation (SA) logic of a typical asynchronous SAR ADC, and provides strategies to reduce both of them. Following these strategies, a unique direct-pass SA logic is proposed based on a full-swing once-triggered DFF and a self-locking tri-state gate. The unnecessary internal switching power of a typical TSPC DFF, which is commonly used in the SA logic, is avoided. The delay of the ready detector as well as the sequencer is removed from the critical path. A prototype SAR ADC based on the proposed SA logic is fabricated in 130 nm CMOS. It achieves a peak SNDR of 56.3 dB at 1.2 V supply and 65 MS/s sampling rate, and has a total power consumption of 555 μ W, while the digital part consumes only 203 μ W.     

A dual mode charge pump with adaptive output used in a class G audio power amplifier

A dual mode charge pump to produce an adaptive power supply for a class G audio power amplifier is presented.According to the amplitude of the input signals,the charge pump has two level output voltage rails available to save power.It operates both in current mode at high output load and in pulse frequency modulation (PFM) at light load to reduce the power dissipation.Also,dynamic adjustment of the power stage transistor size based on load current at the PFM mode is introduced to reduce the output voltage ripple and prevent the switching frequency from audio range.The prototype is implemented in 0.18μm 3.3 V CMOS technology.Experimental results show that the maximum power efficiency of the charge pump is 79.5%@ 0.5x mode and 83.6%@ lx mode.The output voltage ripple is less than 15 mV while providing 120 mA of the load current at PFM control and less than 18 mV while providing 300 mA of the load current at current mode control.An analytical model for ripple voltage and efficiency calculation of the proposed PFM control demonstrates reasonable agreement with measured results.     

一种8-b 180KSPS的带有新颖的时域比较器且有效位数7.97的差分逐次逼近模数转换器

This paper presents a differential successive approximation register analog-to-digital converter (SAR ADC) with a novel time-domain comparator design for wireless sensor networks. The prototype chip has been implemented in the UMC 0.18-μ m 1P6M CMOS process. The proposed ADC achieves a peak ENOB of 7.98 at an input frequency of 39.7 kHz and sampling rate of 180 kHz. With the Nyquist input frequency, 68.49-dB SFDR, 7.97-ENOB is achieved. A simple quadrate layout is adopted to ease the routing complexity of the common-centroid symmetry layout. The ADC maintains a maximum differential nonlinearity of less than 0.08 LSB and integral nonlinearity less than 0.34 LSB by this type of layout.     

An area-efficient 55 nm 10-bit 1-MS/s SAR ADC for battery voltage measurement

An area-efficient CMOS 1-MS/s 10-bit charge-redistribution SAR ADC for battery voltage measurement in a SoC chip is proposed. A new DAC architecture presents the benefits of a low power approach without applying the common mode voltage. The threshold inverter quantizer(TIQ)-based CMOS Inverter is used as a comparator in the ADC to avoid static power consumption which is attractive in battery-supply application. Sixteen level-up shifters aim at converting the ultra low core voltage control signals to the higher voltage level analog circuit in a 55 nm CMOS process. The whole ADC power consumption is 2.5 mW with a maximum input capacitance of 12 pF in the sampling mode. The active area of the proposed ADC is 0.0462 mm2 and it achieves the SFDR and ENOB of 65.6917 dB and 9.8726 bits respectively with an input frequency of 200 kHz at 1 MS/s sampling rate.     

A power-efficient 12-bit analog-to-digital converter with a novel constant-resistance CMOS input sampling switch

Apower-efficient 12-bit40-MS/spipelineanalog-to-digitalconverter（ADC）implementedina0.13 μm CMOS technology is presented. A novel CMOS bootstrapping switch, which offers a constant on-resistance over the entire input signal range, is used at the sample-and-hold front-end to enhance the dynamic performance of the pipelined ADC. By implementing with 2.5-bit-per-stage and a simplified amplifier sharing architecture between two successive pipeline stages, a very competitive power consumption and small die area can be achieved. Meanwhile, the substrate-biasing-effect attenuated T-type switches are introduced to reduce the crosstalk between the two op- amp sharing successive stages. Moreover, a two-stage gain boosted recycling folded cascode （RFC） amplifier with hybrid frequency compensation is developed to further reduce the power consumption and maintain the ADC＇s performance simultaneously. The measured results imply that the ADC achieves a spurious-free dynamic range （SFDR） of 75.7 dB and a signal-to-noise-plus-distortion ratio （SNDR） of 62.74 dB with a 4.3 MHz input signal; the SNDR maintains over 58.25 dB for input signals up to 19.3MHz. The measured differential nonlinearity （DNL） and integral nonlinearity （INL） are -0.43 to ＋0.48 LSB and -1.62 to ＋ 1.89 LSB respectively. The prototype ADC consumes 28.4 mW under a 1.2-V nominal power supply and 40 MHz sampling rate, transferring to a figure- of-merit （FOM） of 0.63 pJ per conversion-step.     

A robust and simple two-mode digital calibration technique for pipelined ADC

This paper presents a two-mode digital calibration technique for pipelined analog-to-digital converters (ADC).The proposed calibration eliminates the errors of residual difference voltage induced by capacitor mismatch of pseudorandom(PN) sequence injection capacitors at the ADC initialization,while applies digital background calibration to continuously compensate the interstage gain errors in ADC normal operation.The presented technique not only reduces the complexity of analog circuit by eliminating the implementation of PN sequence with accurate amplitude in analog domain,but also improves the performance of digital background calibration by minimizing the sensitivity of calibration accuracy to sub-ADC errors.The use of opamps with low DC gains in normal operation makes the proposed design more compatible with future nanometer CMOS technology.The prototype of a 12-bit 40-MS/s pipelined ADC with the two-mode digital calibration is implemented in 0.18-μm CMOS process.Adopting a simple telescopic opamp with a DC gain of 58-dB in the first stage,the measured SFDR and SNDR within the first Nyquist zone reach 80-dB and 66-dB,respectively.With the calibration,the maximum integral nonlinearity (INL) of the ADC reduces from 4.75-LSB to 0.65-LSB,while the ADC core consumes 82-mW at 3.3-V power supply.     

A low power 12-bit 200-kS/s SAR ADC with a differential time domain comparator

A low power 12-bit 200-kS/s SAR ADC is proposed.This features a differential time domain comparator whose offset is cancelled by using a charge pump and a phase frequency detector instead of the preamplifiers usually needed in a high resolution comparator.The proposed ADC is manufactured in 0.18-μm CMOS technology and the measured SNR and SNDR are 62.5 dB and 59.3 dB,respectively,with a power consumption of 72μW at a 200-kS/s sampling rate.The device operates with a 1.8-V power supply and achieves a FOM of 477 fJ/conversion-step.     

陷阱俘获存储器中电荷积累过程对保持特性的影响

本文通过数值模拟的方法对陷阱俘获存储器单元在多次擦写过程中的电荷积累过程进行了分析。由于多次擦写后陷阱电荷的积累,电荷之间的复合过程成为一个重要的问题。分析结果显示擦写过程中积累的空穴会对存储器的保持特性产生影响,同时在分析器件保持特性的时候电荷之间的复合机制必须加以考虑。     

Effect of trapped charge accumulation on the retention of charge trapping memory

The accumulation process of trapped charges in a TANOS cell during P/E cycling is investigated via numerical simulation.The recombination process between trapped charges is an important issue on the retention of charge trapping memory.Our results show that accumulated trapped holes during P/E cycling can have an influence on retention,and the recombination mechanism between trapped charges should be taken into account when evaluating the retention capability of TANOS.     

A novel modified charge pumping method for trapped charge characterization in nanometer-scale devices

A new modified method based on the charge pumping technique is proposed and adopted to extract the lateral profiles of oxide charges in an advanced MOSFET.A 0.12μm SONOS device with 50 nm threshold voltage peak is designed and utilized to demonstrate the proposed method.The trapped charge distribution with a narrow peak can be precisely characterized with this method,which shows good consistency with the measured threshold voltage.     

程控交换机计费系统的设计

本文采用计费系统的通用计算模型，提出了计费，分拣及月结一体化（也可分离）的程控交换机计费系统的设计思想，并给出了一种实际实现的计费系统。     

低频率电荷泵锁相环设计

设计一款音频范围内的电荷泵锁相环,采用动态D触发器鉴频鉴相器及电流舵差分输入电荷泵。压控振荡器采用了对电容充放电的形式产生震荡波形,实现低频输出。采用HHNEC BCD035工艺并用Cadence软件实现仿真,实现250 kHz频率锁定,锁定时间为80μs,锁定时相位差为75 ns且压控振荡器控制电压纹波为5 mV。     

一种应用于纳米尺度器件陷阱电荷表征的新型改进电荷泵方法

随着器件特征尺寸的缩小,热载流子带来的器件蜕化效应越来越严重。电荷泵方法可用于表征陷阱电荷的分布。但由于局部阈值电压窄峰的影响,传统电荷泵法在测试陷阱电荷分布时存在误差。本文提出了一种改进型电荷泵测试方法,可用于精确提取纳米尺度器件中陷阱电荷的横向分布。 本文采用0.12微米的SONOS器件来验证这一方法的有效性。通过编程控制,使SONOS器件形成大约50纳米的阈值电压窄峰。采用新方法测试得到的陷阱电荷分布与测试得到的阈值电压有较好的一致性。     

低电源电压条件下的双阈值电压泵

由于存在逆向电流,利用电流传输开关特性的改进型的电压泵（NCP-1）的电压增益被大大减弱.本论文提供了一个新的方法.通过使用双阈值电压CMOS代替单阈值电压CMOS,不但消除了逆向电流,而且对低电压有很好的放大增益.PSPICE模拟结果,当电源电压为0.5V时,6级电压泵可使输出电压放大到2.68V.     

共轭点电荷系在静电劈形问题中的应用

根据点-面情形电像解的规律提出共轭点电荷系概念,对不同类型的共轭点电荷系在半无限大导体平面上的感应电荷总量进行了计算,并应用到有一定对称性分布的静电劈形问题中。共轭点电荷系思想对π是夹角整数倍情形时的劈形角平分面上点电荷的电像解提供了一种新的解法和思路。     

生物电荷转移效应的分子动力学模拟

本文介绍了用分子动力学模拟肌红蛋白中的铁离子和周围的水阴离子发生电荷转移的动力学过程,并进一步讨论了该过程的微观机制——讨论短程势、长程库仑势和水效应对弛豫过程的影响.     

A novel SOI high-voltage SJ-pLDMOS based on self-adaptive charge balance

A new SOl self-balance （SB） super-junction （S J） pLDMOS with a self-adaptive charge （SAC） layer and its physical model are presented. The SB is an effective way to realize charges balance （CB）. The substrate-assisted depletion （SAD） effect of the lateral SJ is eliminated by the self-adaptive inversion electrons provided by the SAC. At the same time, high concentration dynamic self-adaptive electrons effectively enhance the electric field （EI） of the dielectric buried layer and increase breakdown voltage （BV）. E1 = 600 V/μm and BV =- 237 V are obtained by 3D simulation on a 0.375-μm-thick dielectric layer and a 2.5-μm-thick top silicon layer. The optimized structure realizes the specific on resistance （Ron,sp） of 0.01319Ω·cm2, FOM （FOM = BV2/R p） of 4.26 MW/cm2 under a 11 μm length （Ld） drift region.