一种低延迟低功耗的片上全局互连方法

提出了一种用于片上全局互连的混合插入方法. 该方法利用中继驱动器和低摆幅差分信号电路在驱动不同长度连线时的优点，将它们混合插入到连线的合适位置，从而降低互连的延时和功耗. 模拟结果表明，该方法与已有方法相比在延时、能耗、能耗延时积以及面积等方面都获得了一定程度的改善.     

Information raining and optimal link-layer design for mobile hotspots

In this paper, we propose a link layer design for mobile hotspots. We design a novel system architecture that enables high-speed Internet access in railway systems. The proposed design uses a number of repeaters placed along the track and multiple antennas installed on the roof of a vehicle. Each packet is decomposed into smaller fragments and relayed to the vehicle via adjacent repeaters. We also use erasure coding to add parity fragments to original data. This approach is called information raining since fragments are rained upon the vehicle from adjacent repeaters. We investigate two instances of information raining. In blind information raining, all repeaters awaken when they sense the presence of the vehicle. The fragments are then blindly transmitted via awakened repeaters. A vehicle station installed inside the train is responsible for aggregating a large enough number of fragments. In the throughput-optimized information raining, the vehicle station selects a bipartite matching between repeaters and roof-top antennas and activates only a subset of the repeaters. It also dictates the amount of transmission power of each activated repeater. Both the bipartite matching and power allocations are individually shown to be NP-complete. Matching heuristics based on the Hungarian algorithm and Gale-Shapley algorithm are proposed. A simplex-type algorithm is proposed as the power allocation heuristics.     

A Baseband Hybrid Digital Transmission Scheme

A baseband hybrid digital transmission scheme is studied, and it is shown that the low- and high-frequency cutoffs in analog repeaters extremely degrade signal waveforms. Solutions studied are a combination of dc-constrained coding and modification of amplitude-frequency characteristics for low-frequency distortion, and a combination of flat amplitude equalization and simple phase equalization for high-frequency distortion. It is shown that these solutions reduce waveform distortions by a factor of ten. A solution of the control problem for automatic gain control (AGC) is also presented.     

100 dB optical path loss transmission system experiment employing two linear optoelectronic repeaters

Linear optoelectronic amplification is investigated as an economic option for the provision of sufficient optical gain for fibre transmission systems of several hundred km lengths. Experimental results are presented demonstrating a system span capability in excess of 100 dB at 420 Mbit/s and 1.55 mu m wavelength with two intermediate linear repeaters. Extensions of the technique to higher line-rates and larger numbers of repeaters are discussed.<>     

Obtaining schedules for digital systems

A systematic technique is presented to derive correct schedules for a synchronous digital system, given a signal flow graph for an algorithm. It is also shown how to use this technique to derive designs that are optimal in having the lowest latency, the highest throughput, or the smallest number of registers. The same technique can also be used to verify digital systems that have already been designed     

High-speed signal processing using systolic arrays over finiterings

A modular architecture for very fast digital signal processing (DSP) elements are presented. The computation is performed over finite rings (or fields) and is able to emulate processing over the integer ring using residue number systems. The computations are restricted to closed operations (ring or field binary operators) with the ability to perform limited scaling operations. Computations naturally defined over finite mathematical systems are also easily implemented using this approach. The technique evolves from the decomposition of each closed calculation using the ring/field associativity property. Linear systolic arrays, formed with multiple elements, each of a single generic form, are used for all calculations. The pipeline cycle is determined from the generic cell and is predicted to be very fast by a critical path analysis. The cells are matched to the VLSI medium, and the resulting array structures are very dense. Examples of DSP applications are given to illustrate the technique, and example cell and array VLSI layouts are presented for a 3-μm CMOS process     

Differential current-sensing for on-chip interconnects

This paper presents a differential current-sensing technique as an alternative to existing circuit techniques for on-chip interconnects. Using a novel receiver circuit, it is shown that, delay-optimal current-sensing is a faster (20% on an average) option as compared to the delay-optimal repeater insertion technique for single-cycle wires. Delay benefit for current-sensing increases with an increase in wire width. Unlike repeaters, current-sensing does not require placement of buffers along the wire, and hence, eliminates any placement constraints. Inductive effects are negligible in differential current-sensing. Current-sensing also provides a tighter bound on delay with respect to process variations. However, current-sensing has some drawbacks. It is power inefficient due to the presence of static-power dissipation. Current-sensing is essentially a low-swing signaling technique, and hence, it is sensitive to full swing aggressor noise.     

基于UT1553BCRTM协议芯片的GJB289A通信接口

GJB289A总线具有很高的可靠性和灵活性,广泛应用于航空航天等领域。本文提出基于Aeroflex公司UT1553BCRTM协议芯片实现的GJB289A通信接口,完成了BC和RT的基本功能,支持同步通信和异步通信。文中对同步通信采用传统的静态总线控制协议,采用一种改进的静态总线控制技术,对非周期消息的异步通讯进行了详细说明。本设计有效地改善了GJB289A总线中非周期消息的传输延迟,保证了消息通讯的实时性。     

3-D ICs: a novel chip design for improving deep-submicrometerinterconnect performance and systems-on-chip integration

Performance of deep-submicrometer very large scale integrated (VLSI) circuits is being increasingly dominated by the interconnects due to decreasing wire pitch and increasing die size. Additionally, heterogeneous integration of different technologies in one single chip is becoming increasingly desirable, for which planar (two-dimensional) ICs may not be suitable. This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel three-dimensional (3-D) chip design strategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize a system-on-a-chip (SoC) design. A comprehensive analytical treatment of these 3-D ICs has been presented and it has been shown that by simply dividing a planar chip into separate blocks, each occurring a separate physical level interconnected by short and vertical interlayer interconnects (VILICs), significant improvement in performance and reduction in wire-limited chip area can be achieved, without the aid of any other circuit or design innovations. A scheme to optimize the interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis for a two-layer 3-D chip. Furthermore, one of the major concerns in 3-D ICs arising due to power dissipation problems has been analyzed and an analytical model has been presented to estimate the temperatures of the different active layers. It is demonstrated that advancement in heat sinking technology will be necessary in order to extract maximum performance from these chips. Implications of 3-D device architecture on several design issues have also been discussed with special attention to SoC design strategies. Finally some of the promising technologies for manufacturing 3-D ICs have been outlined     

Long-haul high-speed optical communication systems using asemiconductor laser amplifier

High-speed long-haul systems using semiconductor laser amplifiers, which eliminate the need for high-speed electronics in repeaters and are transparent to the transmission speed are considered for application in undersea high-speed transmission systems. The potential of laser-amplifier-repeated transmission systems has been explored by transmission experiments, showing that a high-speed system above 2 Gb is possible by filtering out the spontaneous emission power of the laser amplifier. A theoretical estimation of SNR degradation due to noise accumulation of chained laser amplifiers shows that systems are possible, using 30 to 40 laser amplifier repeaters, if narrow-bandwidth optical filters are used     

Recent progress in amplified undersea systems

The advent of the optical amplifiers has removed the loss limitation of the fiber in the conventional undersea systems using 3R (retiming, reshaping, regenerating) repeaters, and it has introduced new design criteria for the undersea lightwave systems. The accumulation of the small impairment factors that was negligible in the conventional system becomes significant to determine the transmission performances of the amplified system. The fiber nonlinearity is a distinctive limitation factor that dominates the transmission performance of the amplified system, although it was not a limitation factor in the conventional system. This paper describes the recent progress of the undersea lightwave cable systems employing optical amplifier repeaters. The limitation factors and the polarization dependent characteristics of the amplified system are described. The system demonstrations with conventional IM-DD technology are presented using both recirculating loop and straight fiber transmission line. The system maintenance method is also explained briefly. Future technologies adopting the WDM or the optical solitons are also discussed     

Effects of inductance on the propagation delay and repeaterinsertion in VLSI circuits

A closed-form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range of RLC loads. It is shown that the error in the propagation delay if inductance is neglected and the interconnect is treated as a distributed RC line can be over 35% for current on-chip interconnect. It is also shown that the traditional quadratic dependence of the propagation delay on the length of the interconnect for RC lines approaches a linear dependence as inductance effects increase. On-chip inductance is therefore expected to have a profound effect on traditional high-performance integrated circuit (IC) design methodologies. The closed-form delay model is applied to the problem of repeater insertion in RLC interconnect. Closed-form solutions are presented for inserting repeaters into RLC lines that are highly accurate with respect to numerical solutions. RC models can create errors of up to 30% in the total propagation delay of a repeater system as compared to the optimal delay if inductance is considered. The error between the RC and RLC models increases as the gate parasitic impedances decrease with technology scaling. Thus, the importance of inductance in high-performance very large scale integration (VLSI) design methodologies will increase as technologies scale     

基于同步并行结构的视频处理IP模块的VLSI设计

本文在讨论隔行视频信号的逐行处理算法的VLSI实现和视频信号的色度处理和色度空间转换的硬件实现基础上,针对视频信号处理实时性,并发性以及运算量大的特点,提出了基于同步并行流水线的VLSI结构.同时结合SOC的IP模块设计给出相应的硬件实现算法.该设计已基于0.35μm CMOS工艺标准单元库进行了综合验证.     

Linearization of Multichannel Analog Optical Transmitters by Quasi-Feedforward Compensation Technique

A quasi-feedforward compensation technique is described for linearization of LED's in analog fiber optics based video transmission systems, Experimentally we have observed an improvement of more than 35 dB in second-order and 20 dB in third-order distortion in a system transmitting three TV channels simultaneously. The linearized system is capable of video signal transmission over a distance of at least 2 km without repeaters.     

Ultrahigh-speed HEMT LSI technology for supercomputer

The current status of high electron mobility transistor (HEMT) technology at Fujitsu for high-performance VLSI is presented, focusing on device performance in the submicrometer dimensional range and the HEMT LSIs implemented in supercomputer systems. The HEMT is a very promising device for ultrahigh-speed LSI/VLSI applications because of the high-mobility GaAs/AlGaAs heterojunction structure. A 1.1 K-gate bus-driver logic LSI has been developed to demonstrate the high-speed data transfer in a high-speed parallel processing system at room temperature, operating at 10.92 GFLOPS. A cryogenic 3.3 K-gate random number generator logic LSI with maximum clock frequency of 1.6 GHz has also been developed to demonstrate the high-clock-rate system operations at liquid-nitrogen temperature. For VLSI level complexity, a HEMT 64-kb static RAM with 1.2-ns access operation and a 45 K-gate gate array with 35-ps logic delay have been developed operating at room temperature, demonstrating the high performance required for future high-speed computer systems     

Minimization of delay and crosstalk in high-speed VLSIinterconnects

Design optimization of time responses of high-speed VLSI interconnects modeled by distributed coupled transmission line networks is presented. The problem of simultaneous minimization of crosstalk, delay and reflection is formulated into minimax optimization. Design variables include physical/geometrical parameters of the interconnects and parameters in terminating/matching networks. A recently published simulation and sensitivity analysis technique for multiconductor transmission lines is expanded to directly address the VLSI interconnect environment. The new approach permits efficient physical/geometrical oriented interconnect design using exact gradient based minimax optimization. Examples of interconnect optimization demonstrate significant reductions of crosstalk, delay, distortion and reflection at all vital connection ports. The technique developed is an important step towards optimal design of circuit interconnects for high-speed digital computers and communication systems     

A comprehensive 2-D inductance modeling approach for VLSI interconnects: frequency-dependent extraction and compact circuit model synthesis

Although three-dimensional (3-D) partial inductance modeling costs have decreased with stable, sparse approximations of the inductance matrix and its inverse, 3-D models are still intractable when applied to full chip timing or crosstalk analysis. The 3-D partial inductance matrix (or its inverse) is too large to be extracted or simulated when power-grid cross-sections are made wide to capture proximity effect and wires are discretized finely to capture skin effect. Fortunately, 3-D inductance models are unnecessary in VLSI interconnect analysis. Because return currents follow interconnect wires, long interconnect wires can be accurately modeled as two-dimensional (2-D) transmission lines and frequency-dependent loop impedances extracted using 2-D methods . Furthermore, this frequency dependence can be approximated with compact circuit models for both uncoupled and coupled lines. Three-dimensional inductance models are only necessary to handle worst case effects such as simultaneous switching in the end regions. This paper begins by explaining and defending the 2-D modeling approach. It then extends the extraction algorithm to efficiently include distant return paths. Finally, a novel synthesis technique is described that approximates the frequency-dependent series impedance of VLSI interconnects with compact circuit models suitable for timing and noise analysis.     

Power Consumption of Fault Tolerant Busses

On-chip interconnects in very deep submicrometer technology are becoming more sensitive and prone to errors caused by power supply noise, crosstalk, delay variations and transient faults. Error-correcting codes (ECCs) can be employed in order to provide signal transmission with the necessary data integrity. In this paper, the impact of ECCs to encode the information on a very deep submicrometer bus on bus power consumption is analyzed. To fulfill this purpose, both the bus wires (with mutual capacitances, drivers, repeaters and receivers) and the encoding-decoding circuitry are accounted for. After a detailed analysis of power dissipation in deep submicrometer fault-tolerant busses using Hamming single ECCs, it is shown that no power saving is possible by choosing among different Hamming codes. A novel scheme, called dual rail, is then proposed. It is shown that dual rail, combined with a proper bus layout, can provide a reduction of energy consumption. In particular, it is shown how the passive elements of the bus (bottom and mutual wire capacitances), active elements of the bus (buffers) and error-correcting circuits contribute to power consumption, and how different tradeoffs can be achieved. The analysis presented in this paper has been performed considering a realistic bus structure, implemented in a standard 0.13-mum CMOS technology.     

GaP planar monolithic matrix-addressable displays

Display systems that are small in size and require a high density of light-emitting elements can be based on light-emitting diodes. Matrix addressing can be used to minimize the external wires. Interconnections on the display plane can be minimized by the use of a monolithic matrix-addressable display device. A planar processing technique which permits the integration of the light-emitting diode interconnections for a monolithic semiconductor array is presented. The operation of a 5 × 7 monolithic matrix-addressable display device is discussed and demonstrated.     

Statistical analysis of timing rules for high-speed synchronousVLSI systems

Timing skew has been the major limitation for high-speed synchronous operation of a VLSI system. In this paper, a statistical timing model that accounts for both static and random timing skew is proposed. Based on this model, we analyze the timing rules of a synchronous VLSI system consisting of multiple pipelined stages, establish the yield of the system as a function of its device characteristics, and derive the relationship between the maximum throughput of such a system and its timing skew. The following timing schemes are evaluated: conventional pipelining, in which the transmitter cannot initiate the next cycle until the receiver has received the data and wave pipelining, in which the transmitter initiates the next cycle as soon as the current data has been sent out. The results show that the yield of a VLSI system using either of the pipelining schemes exhibits threshold behavior for Gaussian distributed static skew. Furthermore, the system throughput is shown to be very sensitive to the random skew