SCR device fabricated with dummy-gate structure to improve turn-on speed for effective ESD protection in CMOS technology

Turn-on speed is the main concern for an on-chip electrostatic discharge (ESD) protection device, especially in the nanoscale CMOS processes with ultrathin gate oxide. A novel dummy-gate-blocking silicon-controlled rectifier (SCR) device employing a substrate-triggered technique is proposed to improve the turn-on speed of an SCR device for using in an on-chip ESD protection circuit to effectively protect the much thinner gate oxide. The fabrication of the proposed SCR device with dummy-gate structure is fully process-compatible with general CMOS process, without using an extra mask layer or adding process steps. From the experimental results in a 0.25-/spl mu/m CMOS process with a gate-oxide thickness of /spl sim/50 /spl Aring/, the switching voltage, turn-on speed, turn-on resistance, and charged-device-model ESD levels of the SCR device with dummy-gate structure have been greatly improved, as compared to the normal SCR with shallow trench isolation structure.     

On-chip ESD protection design with substrate-triggered technique for mixed-Voltage I/O circuits in subquarter-micrometer CMOS Process

A new electrostatic discharge (ESD) protection design, by using the substrate-triggered stacked-nMOS device, is proposed to protect the mixed-voltage I/O circuits of CMOS ICs. The substrate-triggered technique is applied to lower the trigger voltage of the stacked-nMOS device to ensure effective ESD protection for the mixed-voltage I/O circuits. The proposed ESD protection circuit with the substrate-triggered technique is fully compatible to general CMOS process without causing the gate-oxide reliability problem. Without using the thick gate oxide, the new proposed design has been fabricated and verified for 2.5/3.3-V tolerant mixed-voltage I/O circuit in a 0.25-/spl mu/m salicided CMOS process. The experimental results have confirmed that the human-body-model ESD level of the mixed-voltage I/O buffers can be successfully improved from the original 3.4 to 5.6 kV by using this new proposed ESD protection circuit.     

Electrostatic discharge protection design for mixed-voltage CMOS I/O buffers

A new electrostatic discharge (ESD) protection circuit, using the stacked-nMOS triggered silicon controlled rectifier (SNTSCR) as the ESD clamp device, is designed to protect the mixed-voltage I/O buffers of CMOS ICs. The new proposed ESD protection circuit, which combines the stacked-nMOS structure with the gate-coupling circuit technique into the SCR device, is fully compatible to general CMOS processes without causing the gate-oxide reliability problem. Without using the thick gate oxide, the experimental results in a 0.35 /spl mu/m CMOS process have proven that the human-body-model ESD level of the mixed-voltage I/O buffer can be successfully increased from the original /spl sim/2 kV to >8 kV by using this proposed ESD protection circuit.     

Complementary-SCR ESD protection circuit with interdigitatedfinger-type layout for input pads of submicron CMOS IC's

A new ESD protection circuit with complementary SCR structures and junction diodes is proposed. This complementary-SCR ESD protection circuit with interdigitated finger-type layout has been successfully fabricated and verified in a 0.6 μm CMOS SRAM technology with the LDD process. The proposed ESD protection circuit can be free of VDD-to-VSS latchup under 5 V VDD operation by means of a base-emitter shorting method. To compensate for the degradation on latching capability of lateral SCR devices in the ESD protection circuit caused by the base-emitter shorting method, the p-well to p-well spacing of lateral BJT's in the lateral SCR devices is reduced to lower its ESD-trigger voltage and to enhance turn-on speed of positive-feedback regeneration in the lateral SCR devices. This ESD protection circuit can perform at high ESD failure threshold in small layout areas, so it is very suitable for submicron CMOS VLSI/ULSI's in high-pin-count or high-density applications     

Lateral SCR devices with low-voltage high-current triggeringcharacteristics for output ESD protection in submicron CMOS technology

A high-current PMOS-trigger lateral SCR (HIPTSCR) device and a high-current NMOS-trigger lateral SCR (HINTSCR) device with a lower trigger voltage but a higher trigger current are proposed to improve ESD robustness of CMOS output buffer in submicron CMOS technology. The lower trigger voltage is achieved by inserting short-channel thin-oxide PMOS or NMOS devices into the lateral SCR structures. The higher trigger current is achieved by inserting the bypass diodes into the structures of the HIPTSCR and HINTSCR devices. These HIPTSCR and HINTSCR devices have a lower trigger voltage to effectively protect the output transistors in the ESD-stress conditions, but they also have a higher trigger current to avoid the unexpected triggering due to the electrical noise on the output pad when the CMOS ICs are in the normal operating conditions. Experimental results have verified that the trigger current of the proposed HIPTSCR (HINTSCR) is increased up to 225.5 mA (218.5 mA). But, the trigger voltage of the HIPTSCR (HINTSCR) remains at a lower value of 13.4 V (11.6 V). The noise margin against the overshooting (undershooting) voltage pulse on the output pad, without accidentally triggering on the HINTSCR (HIPTSCR), can be greater than VDD+12 V (VSS -12 V). These HIPTSCR and HINTSCR devices have been practically used to protect CMOS output buffers with a 4000-V (700-V) HEM (MM) ESD robustness but only within a small layout area of 37.6×60 μm² in a standard 0.6-μm CMOS technology without extra process modification     

Capacitor-couple ESD protection circuit for deep-submicronlow-voltage CMOS ASIC

Capacitor-couple technique used to lower snapback-trigger voltage and to ensure uniform ESD current distribution in deep-submicron CMOS on-chip ESD protection circuit is proposed. The coupling capacitor is realized by a poly layer right under the wire-bonding metal pad without increasing extra layout area to the pad. A timing-original design model has been derived to calculate the capacitor-couple efficiency of this proposed ESD protection circuit. Using this capacitor-couple ESD protection circuit, the thinner gate oxide of CMOS devices in deep-submicron low-voltage CMOS ASIC can be effectively protected     

Latchup-free ESD protection design with complementary substrate-triggered SCR devices

The turn-on mechanism of silicon-controlled rectifier (SCR) devices is essentially a current triggering event. While a current is applied to the base or substrate of an SCR device, it can be quickly triggered on into its latching state. In this paper, latchup-free electrostatic discharge (ESD) protection circuits, which are combined with the substrate-triggered technique and an SCR device, are proposed. A complementary circuit style with the substrate-triggered SCR device is designed to discharge both the pad-to-V/sub SS/ and pad-to-V/sub DD/ ESD stresses. The novel complementary substrate-triggered SCR devices have the advantages of controllable switching voltage, adjustable holding voltage, faster turn-on speed, and compatible to general CMOS process without extra process modification such as the silicide-blocking mask and ESD implantation. The total holding voltage of the substrate-triggered SCR device can be linearly increased by adding the stacked diode string to avoid the transient-induced latchup issue in the ESD protection circuits. The on-chip ESD protection circuits designed with the proposed complementary substrate-triggered SCR devices and stacked diode string for the input/output pad and power pad have been successfully verified in a 0.25-/spl mu/m salicided CMOS process with the human body model (machine model) ESD level of /spl sim/7.25 kV (500 V) in a small layout area.     

Electrostatic discharge (ESD) protection for CMOS output buffers in scaled-down VLSI technology

To provide area-efficient output ESD protection for the scaled-down CMOS VLSI, a new output ESD protection is proposed. In the new output ESD protection circuit, there are two novel devices, the PTLSCR (PMOS-trigger lateral SCR) and the NTLSCR (NMOS-trigger lateral SCR). The PTLSCR is in parallel and merged with the output PMOS, and the NTLSCR is in parallel and merged with the output NMOS, to provide area-efficient ESD protection for CMOS output buffers. The trigger voltages of PTLSCR and NTLSCR are lowered below the breakdown voltages of the output PMOS and NMOS in the CMOS output buffer. The PTLSCR and NTLSCR are guaranteed to be turned on first before the output PMOS or NMOS are broken down by the ESD voltage. Experimental results have shown that the PTLSCR and NTLSCR can sustain over 4000 V (700 V) of the human-body-model (machine-model) ESD stresses within a very small layout area in a 0.6 μm CMOS technology with LDD and polycide processes. The noise margin of the proposed output ESD protection design is greater than 8 V (lower than −3.3 V) to avoid the undesired triggering on the NTLSCR (PTLSCR) due to the overshooting (undershooting) voltage pulse on the output pad when the IC is under normal operating conditions with 5 V VDD and 0 V VSS power supplies.     

应用于片上ESD防护中新式直通型MOS触发SCR器件的研究

在基于0.13μm CMOS工艺制程下,为研究片上集成电路ESD保护,对新式直通型MOS触发SCR器件和传统非直通型MOS触发SCR进行了流片验证,并对该结构各类特性进行了具体研究分析。实验采用TLP(传输线脉冲)对两类器件进行测试验证,发现新式直通型MOS触发SCR结构要比传统非直通型MOS触发SCR具有更低的触发电压、更小的导通电阻、更好的开启效率以及更高的失效电流。     

0.18μm RF CMOS双向可控硅ESD防护器件的研究(英文)

基于传统双向可控硅(DDSCR)提出了两种静电放电(ESD)保护器件,可应对正、负ESD应力从而在2个方向上对电路进行保护。传统的DDSCR通过N-well与P-well之间的雪崩击穿来触发,而提出的新器件则通过嵌入的NMOS/PMOS来改变触发机制、降低触发电压。两种改进结构均在0.18μmRFCMOS下进行流片,并使用传输线脉冲测试系统进行测试。实验数据表明,这两种新器件具有低触发电压、低漏电流(～nA),抗ESD能力均超过人体模型2kV,同时具有较高的维持电压(均超过3.3V),可保证其可靠地用于1.8V、3.3V I/O端口而避免出现闩锁问题。     

Implementation of Initial-On ESD Protection Concept With PMOS-Triggered SCR Devices in Deep-Submicron CMOS Technology

In order to enhance the applications of SCR devices for deep-submicron CMOS technology, a novel SCR design with "initial-on" function is proposed to achieve the lowest trigger voltage and the highest turn-on efficiency of SCR device for effective on-chip ESD protection. Without using the special native device (NMOS with almost zero or even negative threshold voltage) or any process modification, this initial-on SCR design is implemented by PMOS-triggered SCR device, which can be realized in general CMOS processes. This initial-on SCR design has a high enough holding voltage to avoid latchup issues in a VDD operation voltage of 2.5 V. The new proposed initial-on ESD protection design with PMOS-triggered SCR device has been successfully verified in a fully-silicided 0.25-mum CMOS process     

Optimization on MOS-Triggered SCR Structures for On-Chip ESD Protection

MOS-triggered silicon-controlled rectifier (SCR) devices have been reported to achieve efficient on-chip electrostatic discharge (ESD) protection in deep-submicrometer CMOS technology. The channel length of the embedded MOS transistor in the MOS-triggered SCR device dominates the trigger mechanism and current distribution to govern the trigger voltage, holding voltage, on resistance, second breakdown current, and ESD robustness of the MOS-triggered SCR device. The embedded MOS transistor in the MOS-triggered SCR device should be optimized to achieve the most efficient ESD protection in advanced CMOS technology. In addition, the layout style of the embedded MOS transistor can be adjusted to improve the MOS-triggered SCR device for ESD protection.     

A low-voltage triggering SCR for on-chip ESD protection at outputand input pads

A novel silicon-controlled rectifier (SCR) structure for on-chip protection against electrostatic discharge (ESD) stress at output or input pads is presented. The SCR switches to an ON state at a trigger voltage determined by the gate length of an incorporated nMOS-like structure. Thus, the new SCR can be designed to consistently trigger at a voltage low enough to protect nMOS transistors from ESD. The capability of a protection circuit using the new SCR design is experimentally demonstrated. The tunability of the SCR trigger voltage with reference to the nMOS breakdown voltage is exploited to improve the human body model (HBM) ESD failure threshold of an output buffer from 1500 to 5000 V     

Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-/spl mu/m CMOS process

The turn-on mechanism of a silicon-controlled rectifier (SCR) device is essentially a current triggering event. While a current is applied to the base or substrate of the SCR device, it can be quickly triggered into its latching state. In this paper, a novel design concept to turn on the SCR device by applying the substrate-triggered technique is first proposed for effective on-chip electrostatic discharge (ESD) protection. This novel substrate-triggered SCR device has the advantages of controllable switching voltage and adjustable holding voltage and is compatible with general CMOS processes without extra process modification such as the silicide-blocking mask and ESD implantation. Moreover, the substrate-triggered SCR devices can be stacked in ESD protection circuits to avoid the transient-induced latch-up issue. The turn-on time of the proposed substrate-triggered SCR devices can be reduced from 27.4 to 7.8 ns by the substrate-triggering technique. The substrate-triggered SCR device with a small active area of only 20 /spl mu/m /spl times/ 20 /spl mu/m can sustain the HBM ESD stress of 6.5 kV in a fully silicided 0.25-/spl mu/m CMOS process.     

Substrate-triggered ESD protection circuit without extra process modification

A substrate-triggered technique is proposed to improve electrostatic discharge (ESD) protection efficiency of ESD protection circuits without extra salicide blocking and ESD-implantation process modifications in a salicided shallow-trench-isolation CMOS process. By using the layout technique, the whole ESD protection circuit can be merged into a compact device structure to enhance the substrate-triggered efficiency. This substrate-triggered design can increase ESD robustness and reduce the trigger voltage of the ESD protection device. This substrate-triggered ESD protection circuit with a field oxide device of channel width of 150 /spl mu/m can sustain a human-body-model ESD level of 3250 V without any extra process modification. Comparing to the traditional ESD protection design of gate-grounded nMOS (ggnMOS) with silicide-blocking process modification in a 0.25-/spl mu/m salicided CMOS process, the proposed substrate-triggered design without extra process modification can improve ESD robustness per unit silicon area from the original 1.2 V//spl mu/m/sup 2/ of ggnMOS to 1.73 V//spl mu/m/sup 2/.     

Design of SCR‐Based ESD Protection Circuit for 3.3 V I/O and 20 V Power Clamp

In this paper, MOS‐triggered silicon‐controlled rectifier (SCR)–based electrostatic discharge (ESD) protection circuits for mobile application in 3.3 V I/O and SCR‐based ESD protection circuits with floating diffusion regions for inverter and light‐emitting diode driver applications in 20 V power clamps were designed. The breakdown voltage is induced by a grounded‐gate NMOS (ggNMOS) in the MOS‐triggered SCR‐based ESD protection circuit for 3.3 V I/O. This lowers the breakdown voltage of the SCR by providing a trigger current to the P‐well of the SCR. However, the operation resistance is increased compared to SCR, because additional diffusion regions increase the overall resistance of the protection circuit. To overcome this problem, the number of ggNMOS fingers was increased. The ESD protection circuit for the power clamp application at 20 V had a breakdown voltage of 23 V; the product of a high holding voltage by the floating diffusion region. The trigger voltage was improved by the partial insertion of a P‐body to narrow the gap between the trigger and holding voltages. The ESD protection circuits for low‐ and high‐voltage applications were designed using 0.18 µm Bipolar‐CMOS‐DMOS technology, with 100 µm width. Electrical characteristics and robustness are analyzed by a transmission line pulse measurement and an ESD pulse generator (ESS‐6008).     

Design of Gate‐Ground‐NMOS‐Based ESD Protection Circuits with Low Trigger Voltage,Low Leakage Current,and Fast Turn‐On

In this paper, electrostatic discharge (ESD) protection circuits with an advanced substrate‐triggered NMOS and a gate‐substrate‐triggered NMOS are proposed to provide low trigger voltage, low leakage current, and fast turn‐on speed. The proposed ESD protection devices are designed using 0.13 μm CMOS technology. The experimental results show that the proposed substrate‐triggered NMOS using a bipolar transistor has a low trigger voltage of 5.98 V and a fast turn‐on time of 37 ns. The proposed gate‐substrate‐triggered NMOS has a lower trigger voltage of 5.35 V and low leakage current of 80 pA.     

Ladder-shaped network for ESD protection of millimetre-wave CMOS ICs

A compact ladder-shaped electrostatic discharge (ESD) protection circuit is presented for millimetre-wave integrated circuits (ICs) in CMOS technology. Multiple shorted shunt stubs form a ladder network together with series stubs as ESD protection that discharges current/voltage pulses caused by an ESD event, while at the same time the network is embedded as part of the matching circuit for a normal operation. A 60 GHz low-noise amplifier using a 90 nm CMOS process is demonstrated with the proposed ESD protection methodology that introduces less than 1 dB insertion loss. Owing to the ESD current distribution through multiple shorted stubs, the proposed methodology is useful to millimetre-wave ICs with advanced CMOS technology that suffers from higher sheet resistance of the metal layers.     

Improving ESD protection of 5 V NMOSFET large array device in 0.4 μm BCD process

In the output stage of power ICs, large array devices (LAD) of MOSFETs are usually used to drive a considerable amount of current. Electrostatic discharge (ESD) self-protection capability of LAD is also required. ESD layout rules are usually adopted in low voltage CMOS transistors to improve the ESD performance but with a large layout area. In this paper, a modified RC gate-driven circuit with gate signal control circuit is developed to keep the minimum device layout rule while achieving ESD self-protection. Thus, it results in a very small layout area increment while keeps the LAD operates safely in normal operation and gains good ESD protection level.     

A new on-chip ESD protection circuit with dual parasitic SCRstructures for CMOS VLSI

A new CMOS on-chip electrostatic discharge (ESD) protection circuit which consists of dual parasitic SCR structures is proposed and investigated. Experimental results show that with a small layout area of 8800 μ², the protection circuit can successfully perform negative and positive ESD protection with failure thresholds greater than ±1 and ±10 kV in machine-mode (MM) and human-body-mode (HBM) testing, respectively. The low ESD trigger voltages in both SCRs can be readily achieved through proper circuit design and without involving device or junction breakdown. The input capacitance of the proposed protection circuit is very low and no diffusion resistor between I/O pad and internal circuits is required, so it is suitable for high-speed applications. Moreover, this ESD protection circuit is fully process compatible with CMOS technologies