前栅工艺下高k/金属栅CMOS器件EOT控制技术研究

随着CMOS器件特征尺寸的不断缩小,绝缘栅介质层也按照等比例缩小的原则变得越来越薄,由此而产生的栅漏电流增大和可靠性降低等问题变得越来越严重。传统的SiO2栅介质材料已不能满足CMOS器件进一步缩小的需要,而利用高介电常数栅介质(高k)取代SiO2已成为必然趋势。而在前栅工艺下,SiO2界面层生长问题严重制约了EOT的缩小以及器件性能的提升。介绍了一种前栅工艺下的高k/金属栅结构CMOS器件EOT控制技术,并成功验证了Al元素对SiO2界面层的氧吸除作用。     

基于体硅衬底制作全耗尽FinFET器件的工艺方案

随着MOS器件缩小到纳米尺寸,为了改善器件性能,三维全耗尽FinFET器件受到广泛关注和研究.基于体硅衬底,已实现不同结构的FinFET,如双栅、三栅、环栅等结构.不同于SOI衬底FinFET,对于双栅或三栅结构,体硅衬底制作FinFET可能存在源漏穿通问题,对于环栅FinFET器件,工艺实现是一个很大的挑战.综述了目前解决源漏穿通问题的各种工艺方案,提出了全新的基于体硅衬底制作环栅FinFET的工艺方案,并展示了关键步骤的具体工艺实验结果.     

Au纳米晶MIS结构存储性能研究

从器件结构和能带的角度分析了提高非易失性存储器性能的可能途径,建立了纳米晶浮栅结构的存储模型,并在模型中考虑了量子限制效应对纳米晶存储性能的影响.基于模型计算,分析了纳米晶材料、高k隧穿介质材料及其厚度对纳米晶浮栅结构存储性能的影响.同时,制作了MIS结构(Si/ZrO2/Au Ncs/SiO2/Al)的存储单元,针对该存储单元的电荷存储能力和电荷保持特性进行测试,并对测试结果进行分析.     

体硅衬底上的CMOS FinFET

介绍了一种制作在普通体硅上的CMOS FinFET.除了拥有和原来SOI上FinFET类似的FinFET结构,器件本身在硅衬底中还存在一个凹槽平面MOSFET,同时该器件结构与传统的CMOS工艺完全相容,并应用了自对准硅化物工艺.实验中制作了多种应用该结构的CMOS单管以及CMOS反相器、环振电路,并包括常规的多晶硅和W/TiN金属两种栅电极.分析了实际栅长为110nm的硅基CMOS FinFET的驱动电流和亚阈值特性.反相器能正常工作并且在Vd=3V下201级CMOS环振的最小延迟为146ps/门.研究结果表明在未来VLSI制作中应用该结构的可行性.     

先进的Hf基高k栅介质研究进展

随着CMOS器件特征尺寸的不断缩小,SiO2作为栅介质材料已不能满足集成电路技术高速发展的需求,利用高k栅介质取代SiO2栅介质成为微电子技术发展的必然.但是,被认为最有希望替代SiO2的HfO2由于结晶温度低等缺点,很难集成于现有的CMOS工艺中,新型Hf基高k栅介质的研究成为当务之急.据报道,在HfO2中引入N、Si、Al和Ta可大大改善其热力学稳定性,由此形成的高k栅介质具有优良的电学特性,基本上满足器件的要求.本文综述了这类先进的Hf基高k栅介质材料的最新研究进展.     

绝缘层材料及结构对薄膜晶体管性能的影响

基于半导体仿真软件Silvaco TCAD对薄膜晶体管(TFT)进行器件仿真,并结合实验验证,重点分析不同绝缘层材料及结构对TFT器件性能的影响。仿真及实验所用薄膜晶体管为底栅电极结构,沟道层采用非晶IGZO材料,绝缘层采用SiN_x和HfO_2多种不同组合的叠层结构。仿真及实验结果表明:含有高k材料的栅绝缘层叠层结构较单一SiN_x绝缘层结构的TFT性能更优;对SiN_x/HfO_2/SiN_x栅绝缘层叠层结构TFT,HfO_2取40nm较为合适;对含有高k材料的3层和5层绝缘层叠层结构TFT,各叠层厚度相同的对称结构TFT性能最优。本文通过仿真获得了TFT性能较优的器件结构参数,对实际制备TFT器件具有指导作用。     

GaN基HFET电力电子器件的研究

作为第三代宽禁带半导体器件,GaN基HFET功率器件具耐高压、高频、导通电阻小等优良特性,在电力电子器件方面也具有卓越的优势。概述了基于电力电子方面应用的AlGaN/GaN HFET功率器件的研究进展。从器件的结构入手,介绍了AlGaN/GaN HEMT的研究现状,从栅材料的选取以及栅介质层的结构对器件性能的影响着手,对AlGaN/GaN MIS-HFET的研究进行了详细的介绍。分析了场板改善器件击穿特性的原理以及各种场板结构AlGaN/GaNHFET器件的研究进展。论述了实现增强型器件不同的方法。阐述了GaN基HFET功率器件在材料、器件结构、稳定性、工艺等方面所面临的挑战。最后探讨了GaN基HFET功率器件未来的发展趋势。     

新型金属源／漏工程新进展

当MOSFET器件的栅长缩小到纳米尺度以后,金属源/漏(S/D)结构具有一系列的优点:原子级突变结能够抑制短沟道效应(SCE),低S/D串联电阻和接触电阻,S/D形成的低温工艺适宜集成高k栅介质、金属栅和应变硅等新材料,使之成为掺杂硅S/D结构最有希望的替代者.文章主要介绍形成低肖特基势垒高度(SBH,Schottky Barrier Height)结材料的选择,以及采用杂质分凝、界面工程和应变工程等肖特基势垒调节技术的主要制备工艺和势垒调节机理.     

20纳米nMOS器件中应力金属栅结构设计与薄膜工艺优化

对于如今的CMOS集成工艺,应变金属栅是关键的工艺引入应变技术（PIS,process-induced-strain）之一。在本文中,为了在20nm高K金属栅后栅工艺的nMOS器件中得到较高栅应力,我们对金属栅结构和薄膜工艺的优化进行了大量的研究。通过TCAD工具对工艺和器件的仿真,我们研究了先进应变金属栅技术对器件性能的影响。带有不同栅应力（0GPa~-6GPa）的金属栅电极被应用在器件的仿真中,与此同时,其他PIS技术,如e-SiC 和氮化物应力层也被应用于器件中。随着器件尺寸的减小,应变金属栅对器件中沟道载流子输运有巨大的提高作用。此外,一种新型的角栅电极结构被提出,角度与沟道应力的关系被研究。同时,一种新的全应变金属填充栅以及用平板型氧化铪层代替U型氧化铪层,都能够提高应变金属栅的效果。为了在金属栅中得到更大应力的薄膜,我们优化了物理汽相淀积氮化钛的工艺条件。在氮气流量大约6sccm,较高溅射功率和较薄膜厚的情况下我们得到了最大的压应力-6.5GPa。     

金属栅将取代多晶硅栅

为了克服器件尺寸缩小达到O．lum时,与多晶硅栅和薄栅氧化物有关的诸多问题,如栅耗尽、高阻栅、沟道区内的棚渗透、栅氧化隧道漏泄等等,也许很有必要采用金属栅和高k柳材料。1999年在旧金山召开的国际电子器件会议上,讨论了金属棚和可替换栅介质材料。如东芝公司微电子工程实验室具体介绍了开发生产金属栅的镶嵌工艺,以及工艺中所用到的高介质常数栅绝缘体（Ta刃。）。当浅沟槽隔离（ST）形成后,就进行源／漏注入,与用生长在虚拟棚氧化物上的SIP4／多晶硅薄膜制作的虚拟栅自对准。用LPCVD淀积预金属介质膜SIO。,并用CMP平面…     

On the Suitability of a High- $k$ Gate Dielectric in Nanoscale FinFET CMOS Technology

The impact of a high-k gate dielectric on the device and circuit performances of nanoscale double-gate (DG) FinFET CMOS technology is examined via physics-based device/circuit simulations. DG FinFETs are designed with high k at the high- performance 45-nm node of the 2005 Semiconductor Industry Association International Technology Roadmap for Semiconductors (ITRS; L_g = 18 nm), and are compared with a pragmatic design in which the traditional SiON (or SiO₂) gate dielectric is retained and kept relatively thick to avoid excessive gate tunneling current. Whereas it is presumed that a high-k dielectric, if and when adequately integrated, will significantly enhance CMOS scalability and performance, we show that there are heretofore unacknowledged compromising effects associated with it that undermine this enhancement. In fact, our results show that for DG FinFET CMOS, a high-k gate dielectric actually undermines speed performance while giving little improvement in scalability relative to the pragmatic design, whereas the latter can be scaled, with good performance, to the end of the ITRS.     

Subthreshold analysis of nanoscale FinFETs for ultra low power application using high-k materials

Fin Field Effect Transistors (FinFETs) are used for Complementary Metal Oxide Semiconductor applications beyond the 45?nm node of the Semiconductor Industry Association (SIA) roadmap because of their excellent scalability and better immunity to short channel effects. This article examines the impact of high-k dielectrics on FinFETs. The FinFET device performance is analysed for On Current, Off Current, I _on/I _off ratio, drain induced barrier lowering, electrostatic potential along the channel, electric field along the channel, transconductance, output resistance, intrinsic gain, gate capacitance and transconductance generation factor, by replacing the conventional silicon dioxide gate dielectric material, with various high dielectric constant materials. Nanosize ZrO₂ (zirconium-di-oxide) is found out to be the best alternative for SiO₂ (silicon-di-oxide). It is also observed that the integration of high-k dielectrics in the devices significantly reduces the short channel effects and leakage current. The suitability of nanoscale FinFETs is observed with the help of an inverter circuit and their gain values are calculated for circuit applications.     

Sub-60-nm quasi-planar FinFETs fabricated using a simplifiedprocess

N-channel double-gate metal-oxide-semiconductor field-effect transistor (MOSFET) FinFETs with gate and fin dimensions as small as 30 nm have been fabricated using a new, simplified process. Short channel effects are effectively suppressed when the Si fin width is less than two-thirds of the gate length. The drive current for typical devices is found to be above 500 μA/μm (or 1 mA/μm, depending on the definition of the width of the double-gate device) for V_g-V _t=V_d=1 V. The electrical gate oxide thickness in these devices is 21 Å, determined from the first FinFET capacitance-versus-voltage characteristics obtained to date. These results indicate that the FinFET is a promising structure for the future manufacturing of integrated circuits with sub-60-nm feature size, and that double-gate MOSFETs can meet international technology roadmap for semiconductors performance specifications without aggressive scaling of the gate-oxide thickness     

Extension and source/drain design for high-performance FinFET devices

Double gate devices based upon the FinFET architecture are fabricated, with gate lengths as small as 30 nm. Particular attention is given to minimizing the parasitic series resistance. Angled extension implants and selective silicon epitaxy are investigated as methods for minimizing parasitic resistance in FinFETs. Using these two techniques high performance devices are fabricated with on-currents comparable to fully optimized bulk silicon technologies. The influence of fin thickness on device resistance and short channel effects is discussed in detail. Devices are fabricated with fins oriented in the <100> and <100> directions showing different transport properties.     

The Potential of FinFETs for Analog and RF Circuit Applications

CMOS downscaling in the nanoscale era will necessitate drastic changes to the planar bulk CMOS transistor to keep pace with the required speed increase while at the same time maintaining acceptable performance in terms of leakage, variability and analog parameters such as gain, noise and linearity. For the gate electrode and the gate dielectric, which classically use polysilicon and with some amount of nitridation, new materials might be needed. Also, a new transistor architecture might be required that deviates from the planar structure. Thanks to their inherent suppression of short-channel effects, reduced drain-induced barrier lowering and good scalability, multi-gate devices such as fin-shaped field-effect transistors (FinFETs) are considered as possible candidates for device scaling at the end of International Technology Roadmap for Semiconductors. As such, they form a first step between a planar architecture and a silicon nanowire. In this paper, we demonstrate with functional prototypes of analog and RF circuits that the combination of a new gate stack with a FinFET transistor architecture outperforms comparable circuit realizations in planar bulk CMOS for low to moderate speed. Further, the FinFETs exhibit less leakage and show less intra-die variability than their planar bulk counterpart. In the microwave and millimeter-wave frequency region, planar bulk CMOS is still superior. The main challenge for FinFET performance in the coming years is the improvement of the maximum cutoff frequency, which is nowadays limited to 100 GHz.     

Reliability of advanced high-k/metal-gate n-FET devices

Hot-carrier degradation and bias-temperature instability of FinFET and fully-depleted SOI devices with high-k gate dielectrics and metal gates are investigated. Thinner SOI results in increased hot-carrier degradation, which can be recovered by junction engineering. FinFETs with (1 1 0) Si active surfaces exhibit degradation of sub-threshold swing after hot carrier stress, indicating generation of interface states. The effect of duty cycle on bias-temperature instability modulates the quasi-steady-state trap occupancy over a broad distribution of electron trapping and de-trapping times. Only the deeper traps remain filled for low duty cycle, and shallower traps are emptied during AC stress.     

FinFET器件总剂量效应研究进展

全面综述鳍式场效应晶体管(FinFET)的总剂量效应,包括辐照期间外加偏置、器件的工艺参数、提高器件驱动能力的特殊工艺、源/漏掺杂类型以及不同栅介质材料和新沟道材料与FinFET总剂量效应的关系。对于小尺寸器件,绝缘体上硅(SOI)FinFET比体硅FinFET具有更强的抗总剂量能力,更适合于高性能抗辐照的集成电路设计。此外,一些新的栅介质材料和一些新的沟道材料的引入,如HfO₂和Ge,可以进一步提高FinFET器件的抗总剂量能力。     

Process and characteristics of modified Schottky barrier (MSB) p-channel FinFETs

A novel modified Schottky barrier p-channel FinFET (MSB FinFET) has been successfully demonstrated previously. In this paper, the detailed process conditions, especially the formation of MSB junctions, has been presented. Device characteristics as well as the geometry effect are also discussed extensively. In the MSB FinFETs fabricated by the two-step silicidation and implant-to-silicide techniques (ITS), an ultrashort and defect-free source/drain extension (SDE) could be formed at a temperature as low as 600/spl deg/C, resulting in excellent electrical characteristics. The ultrashort SDE could effectively thin out the SB width between source/channel during on-state or broaden and elevate it between drain/channel during off-state. A leakage mechanism of MSB FinFETs similar to the conventional ones was identified by the activation energy analysis. Strong fin width dependence of the electrical characteristics was also found in the proposed devices. When the fin width becomes larger than the silicide grain size, the multigrain structure results in a rough front edge of the MSB junction, which in turn degrades the short-channel device performance. This result indicates that the MSB device is suitable for use as FinFET. The low thermal budget of the MSB FinFET relaxes the thermal stability issue for metal gate/high-/spl kappa/ dielectric integration. It is considered that the proposed MSB FinFET is a very promising nanodevice.     

Bulk inversion in FinFETs and implied insights on effective gate width

Relative values of on-state current in undoped-body double-gate (DG) and triple-gate (TG) FinFETs are examined via three-dimensional numerical device simulations. The simulation results reveal significant bulk inversion in the fin bodies, which limits the benefit of the third (top) gate in the TG FinFET and which negates the utility of the commonly defined effective gate width (W/sub eff/=2h/sub Si/+w/sub Si/). Even the concept of W/sub eff/ for the TG FinFET is invalidated, but the proper W/sub eff/ for the DG FinFET is defined. Physical insights attained from the simulations further solidify our notion, based previously on gate layout-area inefficiency, that the third gate is neither desirable nor beneficial.     

Analysis of Geometry-Dependent Parasitics in Multifin Double-Gate FinFETs

This paper analyzes the geometry-dependent parasitic components in multifin double-gate fin field-effect transistors (FinFETs). Parasitic fringing capacitance and overlap capacitance are physically modeled as functions of gate geometry parameters using a conformal mapping method. Also, a physical gate resistance model is presented, combined with parasitic capacitive couplings between source/drain fins and gates. The effects of geometrical parameters on FinFET design under different device configurations are thoroughly studied