一种新材料结构的RTD器件的设计及实现

设计了一种带有Al0.22Ga0.78As/In0.15Ga0.85As/GaAs发射极空间层和GaAs/In0.15Ga0.85As/GaAs量子阱的共振隧穿二极管(RTD)材料结构,并且成功地制作了相应的RTD器件.在室温下,测试了RTD器件的直流特性,计算了RTD器件的峰谷电流比和可资电流密度.在分析器件特性的基础上,指出调整材料结构和优化工艺参数将进一步提高RTD器件的性能.     

利用空气桥技术实现InP基共振遂穿二极管器件

优化设计了InGaAs/AlAs/InP共振遂穿二极管（RTD）材料结构,并用MBE设备在（100）半绝缘InP单晶片上生长了RTD外延材料。利用电子束光刻工艺和空气桥互连技术,制作了InP基RTD器件。并在室温下测试了器件的电学特性：峰值电流密度78kA/cm2,峰谷电流比（PVCR）为7.8。利用空气桥互连技术实现该类器件,在国内尚属首次。     

InP基共振遂穿二极管器件（RTD）研究

我们在实验中对InGaAs/AlAs/InP共振遂穿二极管（RTD）材料结构进行了优化设计,并用MBE设备在(100)半绝缘InP单晶片上生长了RTD外延材料。我们采用电子束光刻工艺和空气桥互连技术,制作了InP基RTD器件。并在室温下测试了器件的电学特性：峰值电流密度24.6kA/cm2,峰谷电流比(PVCR)为8.6。     

不对称势垒对共振隧穿二极管I-V特性的影响

利用Airy函数和传输矩阵方法计算了不对称势垒厚度的InP基AlAs/InGaAs/AlAs DBS结构在偏压情况下的共振透射系数,并通过材料生长和器件工艺制作得到了共振隧穿二极管的直流I-V特性。在峰值电流密度为132kA/cm2下,获得了17.84的电流峰谷比。测试结果还表明不对称势垒厚度的RTD在偏压情况下,当电子从较薄势垒向较厚势垒穿透时,更容易获得高的电流峰谷比,反之可获得较大的负微分电阻电压区域。     

RTD/HEMT串联型RTT的设计与研制

依据RTD/HEMT串联型RTT的概念,设计了RTD/HEMT单片集成材料结构,该结构采用分子束外延技术生长.采用湿法化学腐蚀、金属剥离、台面隔离和空气桥互连技术,研制了RTD/HEMT串联型RTT,并对RTT及RTT中RTD和HEMT的直流特性进行了测试.测试结果表明:在室温下,器件具有明显的栅控负阻特性,正接型RTT的最大峰谷电流之比在2.2左右,反接型RTT的最大峰谷电流之比在4.6左右.实验为RTD/HEMT串联型RTT性能的优化和RTD/HEMT单片集成电路的研制奠定了基础.     

RTD/HEMT串联型RTT的设计与研制

依据RTD/HEMT串联型RTT的概念,设计了RTD/HEMT单片集成材料结构,该结构采用分子束外延技术生长.采用湿法化学腐蚀、金属剥离、台面隔离和空气桥互连技术,研制了RTD/HEMT串联型RTT,并对RTT及RTT中RTD和HEMT的直流特性进行了测试.测试结果表明:在室温下,器件具有明显的栅控负阻特性,正接型RTT的最大峰谷电流之比在2.2左右,反接型RTT的最大峰谷电流之比在4.6左右.实验为RTD/HEMT串联型RTT性能的优化和RTD/HEMT单片集成电路的研制奠定了基础.     

InP材料体系RTD的研制

报道了InP衬底AlAs /In0.53Ga0.47As/AlAs结构共振隧穿二极管(RTD)的研制过程.衬底片选用(001)半绝缘InP单晶片,结构材料使用分子束外延(MBE)技术制备,并用PL谱对外延片进行测试,器件采用台面结构.测得RTD器件室温下的峰谷电流比(PVCR)为7.4,峰值电流密度(Jp)为1.06×105A/cm-2,是国内首例成功的InP材料体系RTD.     

势阱势垒宽度对GaAs/AlGaAs对称DBS RTD NDR特性的影响

目前共振隧穿二极管(RTD)多值逻辑电路研究采用多个MOSFETs组合,以逼近RTD特性,这是现有逻辑功能验证的不足。针对该问题,通过建立对称双势垒RTD电子输运的解析模型,进而采用SILVACO TCAD对Ga As/Al Ga As基对称DBS RTD器件的电学特性进行仿真实验研究。根据仿真实验的结果分析总结了势阱和势垒宽度对Ga As/Al Ga As基对称DBS RTD负阻特性影响的规律,并根据MVL电路设计应用的低压、低功耗、适当峰谷电流比和工艺可实现性等要求,通过大量的仿真优化实验提出采用Ga As/Al Ga As基对称DBS RTD实现多值逻辑电路设计所需的对称DBS RTD器件设计参数窗口。     

子阱及非对称势垒对GaN RTD电学特性的影响

利用Silvaco软件对Al0.2Ga0.8N/GaN共振隧穿二极管(RTD)进行仿真,重点研究了InGaN子量子阱结构及相应非对称势垒结构设计对其电流特性的影响。对比分析了子量子阱结构中InGaN的In组分和子阱厚度对RTD微分负阻(NDR)特性的影响,得出了提升器件性能的最佳参数范围。为了克服Al0.2Ga0.8N/GaN RTD势垒低对器件电流峰谷比(PVCR)的影响,在子量子阱结构的基础上引入了非对称势垒结构设计,通过改变收集区侧势垒的高度和厚度,将AlGaN/GaN的Ip和PVCR由基本结构的0.42 A和1.25,提高到了0.583 A和5.01,实现了器件性能的优化,并为今后的器件研制提供了设计思路。     

谐振隧穿二极管的直流模型及其双稳态特性

研制成的在常温下工作的谐振隧穿二极管(RTD),峰谷比达到了5∶1,最高振荡频率为26.3GHz.采用基于物理意义的电流-电压方程,利用通用电路模拟软件PSPICE,建立了其直流电路模型,模拟结果和实验数据吻合得很好;并以此为基础模拟出了以RTD为驱动器,以电阻或RTD本身为负载的电路双稳态特性,同时分析了RTD器件双稳态特性.     

High performance aluminum arsenic intraband resonant microwave devices

We report on GaAs/AlAs triple-barrier quantum well intraband (TBQWI) heterostructures grown by molecular beam epitaxy (MBE) on n⁺ GaAs substrate. Heterostructure quality was evaluated by X-ray diffraction and photoluminescence spectrum measurements. The position of the broad peak near 65.84° corresponds well to the diffraction from the (4 0 0) face of AlAs layers assuming intensity of total AlAs spacers and barriers. The 10K photoluminescence (PL) data has a strong peak at 8140 Å. The PL spectrum is dominated by a sharp peak centered at the emission energy of 1.52 eV attributed to the energy of e1-hh bond exciton of GaAs layer. TBQWI heterostructures were grown and processed into resonant tunneling diode (RTD). Room temperature electrical measurement of the TBQWI RTD yielded maximum peak to valley current ratio (PVCR) of 120 with peak current density (J_p) of 2.1 kA/cm². The high PVCR of this GaAs/AlAs TBQWI RTD is, to the better of our knowledge, one of the higher PVCRs obtained in any intraband tunnel device.     

Performance analysis of 20 nm gate-length In0.2Al0.8N/GaN HEMT with Cu-gate having a remarkable high ION/IOFF ratio

Abstract： We propose a new structure of InxAll-xN/GaN high electron mobility transistor （HEMT） with gate length of 20 nm. The threshold voltage of this HEMT is achieved as -0.472 V. In this device the InA1N barrier layer is intentionally n-doped to boost the ION/IOFF ratio. The InAlN layer acts as donor barrier layer for this HEMT which exhibits an ION = 10-4.3 A and a very low IOFF = 10-14.4 A resulting in an ION/IoFF ratio of 1010.1. We compared our obtained results with the conventional InAlN/GaN HEMT device having undoped barrier and found that the proposed device has almost l0s times better ION/IOFF ratio. Further, the mobility analysis in GaN channel of this proposed HEMT structure along with DC analysis, C-V and conductance characteristics by using small-signal analysis are also presented in this paper. Moreover, the shifts in threshold voltage by DIBL effect and gate leakage current in the proposed HEMT are also discussed. InAlN was chosen as the most preferred barrier layer as a replacement of AlGaN for its excellent thermal conductivity and very good scalability.     

Electrical properties of SiO2/TiO2 high-k gate dielectric stack

The trapping/detrapping behavior of charge carriers in ultrathin SiO₂/TiO₂ stacked gate dielectric during constant current (CCS) and voltage stressing (CVS) has been investigated. Titanium tetrakis iso-propoxides (TTIP) was used as the organometallic source for the deposition of ultra-thin TiO₂ films at low temperature (<200 °C) on strained-Si/relaxed-Si_0.8Ge_0.2 heterolayers by plasma-enhanced chemical vapor deposition (PECVD) in a microwave (700 W, 2.45 GHz) plasma cavity discharge system at a pressure of 66.67 Pa. Stress-induced leakage current (SILC) through SiO₂/TiO₂ stacked gate dielectric is modeled by taking into account the inelastic trap-assisted tunneling (ITAT) mechanism via traps located below the conduction band of TiO₂ layer. The increase in the gate current density observed during CVS from room temperature up to 125 ^oC has been analyzed and modeled considering both the buildup of charges in the layer as well as the SILC contribution. Trap generation rate and trap cross-section are extracted. A capture cross-section in the range of 10⁻¹⁹ cm² as compared to 10⁻¹⁶ cm² in SiO₂ has been observed. A temperature-dependent trap generation rate and defects have also been investigated using time-dependent current density variation during CVS. The time dependence of defect density variation is calculated within the dispersive transport model, assuming that these defects are produced during random hopping transport of positively charge species in the insulating high-k stacked layers. SILC generation kinetics, i.e. defect generation probability under different injected fluences for various high-constant stress voltages in both polarities have been studied. An empirical relation between trap generation probability and applied stress voltage for various injected fluences has been developed.     

一种高性能InP基谐振隧穿二极管的研制

设计并用分子束外延技术生长了InP基InGaAs/AlAs体系RTD材料,采用传统湿法腐蚀、光学接触式光刻、金属剥离、台面隔离和空气桥互连工艺,研制出了具有优良负阻特性和较高阻性截止频率的InP基RTD单管，器件正向PVCR为17.5,反向PVCR为28,峰值电流密度为56kA/cm^2,采用RNC电路模型进行数据拟合后得到阻性截止频率为82.8GHz，实验为今后更高性能RTD单管的研制,以及RTD与其他高速高频三端器件单片集成电路的设计与研制奠定了基础。     

Fabrication of an AlAs/In0.53Ga0.47As/InAs Resonant Tunneling Diode on InP Substrate for High-Speed Circuit Applications

在InP衬底上采用感应耦合等离子体刻蚀技术制备了高性能的AlAs/In0.53Ga0.47As/InAs共振隧穿二极管.正向偏压下PVCR=7.57,Jp=39.08kA/cm2;反向偏压下PVCR=7.93,Jp=34.56kA/cm2.在未去除测试电极和引线等寄生参数影响下,面积为5μm×5μm的RTD的阻性截止频率为18.75GHz.最后对非对称的I-V特性进行了分析讨论.     

用于高速电路的InP基共振隧穿二极管制作

在InP衬底上采用感应耦合等离子体刻蚀技术制备了高性能的AlAs/In0.53Ga0.47As/InAs共振隧穿二极管.正向偏压下PVCR=7.57,Jp=39.08kA/cm2;反向偏压下PVCR=7.93,Jp=34.56kA/cm2.在未去除测试电极和引线等寄生参数影响下,面积为5μm×5μm的RTD的阻性截止频率为18.75GHz.最后对非对称的I-V特性进行了分析讨论.     

Characteristics of metal-ferroelectric-insulator-semiconductor structure using Sr0.8Bi2.2Ta2O9 and Sr0.8Bi2.2Ta2O9-BaZrO3 for ferroelectric gates

Characteristics of BaZrO₃ (BZO) modified Sr_0.8Bi_2.2Ta₂O₉ (SBT) thin films fabricated by sol-gel method on HfO₂ coated Si substrates have been investigated in a metal-ferroelectric-insulator-semiconductor (MFIS) structure for potential use in a ferroelectric field effect transistor (FeFET) type memory. MFIS structures consisting of pure SBT and doped with 5 and 7 mol% BZO exhibited memory windows of 0.81, 0.82 and 0.95 V with gate voltage sweeps between −5 and +5 V, respectively. Leakage current density levels of 10⁻⁸ A/cm² for BZO doped SBT gate materials were observed and attributed to the metallic Bi on the surface as well as intrinsic defects and a porous film microstructure. The higher than expected leakage current is attributed to electron trapping/de-trapping, which reduces the data retention time and memory window. Further process improvements are expected to enhance the electronic properties of doped SBT for FeFET.     

Investigation of high-K gate stacks with epitaxial Gd2O3 and FUSI NiSi metal gates down to CET=0.86 nm

Novel gate stacks with epitaxial gadolinium oxide (Gd₂O₃) high-k dielectrics and fully silicided (FUSI) nickel silicide (NiSi) gate electrodes are investigated. Ultra-low leakage current densities down to 10^–7 A cm^–2 are observed at a capacitance equivalent oxide thickness of CET=1.8 nm. The influence of a titanium nitride (TiN) capping layer during silicidation is studied. Furthermore, films with an ultra-thin CET of 0.86 nm at a Gd₂O₃ thickness of 3.1 nm yield current densities down to 0.5 A cm⁻² at V_g=+1 V. The extracted dielectric constant for these gate stacks ranges from k=13 to 14. These results emphasize the potential of NiSi/Gd₂O₃ gate stacks for future material-based scaling of CMOS technology.     

Influence of the metal electrode on the characteristics of thermal Ta2O5 capacitors

The effect of various electrodes (Al, W, TiN) deposited by evaporation (Al) and sputtering (W, TiN) on the electrical characteristics of thermal thin film (15-35 nm) Ta₂O₅ capacitors has been investigated. The absolute level of leakage currents, breakdown fields, mechanism of conductivity, dielectric constant values are discussed in the terms of possible reactions between Ta₂O₅ and electrode material as well as electrode deposition process-induced defects acting as electrically active centers. The dielectric constant values are in the range 12-26 in dependence on both Ta₂O₅ thickness and gate material. The results show that during deposition of TiN and Al a reaction that worsens the properties of Ta₂O₅ occurs while there is not an indication for detectable reduction of Ta₂O₅ when top electrode is W, and the leakage current is 5-7 orders of magnitude lower as compared to Al and TiN-electroded capacitors. The high level of leakage current for TiN and Al gate capacitors are related to the radiation defects generated in Ta₂O₅ during sputtering of TiN, and damaged interface at the electrode due to a reaction between Al and Ta₂O₅, respectively. It is demonstrated that the quality of the top electrode affects the electrical characteristics of the capacitors and the sputtered W is found to be the best. The sputtered W gate provides Ta₂O₅ capacitors with a good quality: the current density <7 × 10⁻¹⁰ A/cm² at 1 V (0.7 MV/cm, 15 nm thick Ta₂O₅). W deposition is not accompanied by an introduction of a detectable damage leading to a change of the properties of the initial as-grown Ta₂O₅ as in the case of TiN electrode. Damage introduced during TiN sputtering is responsible for current deterioration (high leakage current) and poor breakdown characteristics. It is concluded that the sputtered W top electrode is a good candidate as a top electrode of storage capacitors in dynamic random access memories giving a stable contact with Ta₂O₅, but sputtering technique is less suitable (favorable) for deposition of TiN as a metal electrode due to the introduction of radiation defects causing both deterioration of leakage current and poor breakdown characteristics.