一种快速准规则LDPC码编码器的硬件实现

LDPC码用迭代概率译码算法能接近香农限,但编码器常具有码长二次方的复杂度。论文介绍了一种基于Q矩阵的准规则LDPC码编码器直接用H矩阵进行设计,简化了H矩阵存储量,采用半并行结构,能进行运算量为线性复杂度的快速编码。编码器在Xilinx Virtex2 XC2V1000上用Verilog语言完成了物理实现。     

基于 Q -矩阵的LDPC码编码器设计

本文给出 Q 矩阵的定义,在此基础上提出由 Q 矩阵构造的LDPC码新码族;研究 Q 矩阵的性质,根据 Q 矩阵的性质和变化形式,提出一种构造稀疏奇偶校验矩阵 H 的算法,同时给出一种基于 Q 矩阵的LDPC码编码器设计算法.模拟仿真表明,采用和积迭代解码算法,在0.5码率,6144码长,10^-5以下误码率时, Q 矩阵LDPC码目前的最好性能达到离香农限1.5dB.本文还研究了快速搜索 Q 矩阵的算法.如果对 Q 矩阵采用离线搜索,在线存储 Q 矢量的方式,可使构造 H 矩阵的计算复杂度为零,编码器算法复杂度与编码长度N成线性关系. Q 矩阵LDPC码不同于现有其它结构LDPC码的独特之处在于,对码长和码率参数的设计具有高度灵活性,使其能与现有标准兼容.     

LDPC码全并行译码器的设计与实现

本论文用可编程逻辑器件(FPGA)实现了一种低密度奇偶校验码(LDPC)的编译码算法.采用基于Q矩阵LDPC码构造方法,设计了具有线性复杂度的编码器. 基于软判决译码规则,采用全并行译码结构实现了码率为1/2、码长为40比特的准规则LDPC码译码器,并且通过了仿真测试.该译码器复杂度与码长成线性关系,与Turbo码相比更易于硬件实现,并能达到更高的传输速率.     

基于矩阵分块的LDPC码快速编码结构研究

低密度奇偶校验(LDPC)码由于具有接近香农限的性能和高速并行的译码结构而成为研究热点。然而,当码长很长时,编译码器的硬件实现变得很困难。文章从编译码实际实现的角度出发,提出一种基于分块的LDPC码下三角形校验矩阵结构,降低了编译码复杂度,不仅可以实现线性时间编码,同时还可以实现部分并行译码。仿真结果表明,具有这种结构的LDPC码和随机构造的LDPC码相比具有同样好的纠错性能。     

基于范德蒙矩阵的LDPC码构造

对准循环Q矩阵和完全循环差集进行了研究,在此基础上提出了一种LDPC码码族的代数构造方法.采用准循环Q阵为子矩阵,母矩阵采用范德蒙矩阵.母矩阵首行子矩阵利用循环差集进行随机选择.最终生成校验矩阵H.由于码率、码长等参数可以自由选择,从而使设计的码族具有很好的兼容性.通过Matlab和C联合仿真表明,该方法生成的LDPC码编码相对简单,复杂度基本与码长呈线性关系.AWGN信道下3 dB左右时,BER能够达到10-8数量级并且没有出现误码平台现象.     

GB20600标准的LDPC码的改进

尽管LDPC码已经被GB20600标准采纳作为信道编码,与其它LDPC码相比,在同样码长和码率的情况下,GB20600 LDPC码误码率性能并非最佳;GB20600标准的LDPC码的码长达7493,存在编码复杂性问题,但是GB20600 LDPC码未采用基于校验矩阵的快速算法,这给GB20600 LDPC编解码器的硬件实现带来较大的困难。本文在现有GB20600 LDPC码的设计框架下,对GB20600中LDPC码的校验矩阵进行了修改,在此基础上提出一种有效的LDPC码的快速迭代算法,使编解码器的硬件易于实现。改进后的LDPC码的编码算法具有较低的实现复杂度。仿真结果表明,改进后的LDPC码的误包率性能优于现GB20600中LDPC码的误包率性能。      

一种快速编码的半随机LDPC码构造研究

低密度奇偶校验码(LDPC码)具有逼近Shannon限的优异纠错性能,在信道编码领域的应用越来越广泛,但是LDPC码的编码复杂性一直是制约其普遍应用的突出问题。奇偶校验矩阵的结构则直接决定着LDPC码的编码复杂度和译码性能。提出一种准双对角线结构的半随机LDPC码奇偶校验矩阵的构造方法,它具有IEEE 802.16e标准LDPC码的优异纠错性能和低编码复杂度,同时在码率、码长、基础校验矩阵和扩展因子等设计方面更具灵活性,能更好地适应工程实践的需要。采用这种构造方法,以(16 384,8 192)LDPC码为例进行快速迭代编码,能够获得优异的译码性能,可以用于实现高速率低复杂度的LDPC译码器设计。     

具有低编码复杂度准循环扩展LDPC码的构造方法

PEG(Progressive-Edge-Growth)算法是迄今为止构造性能优异的LDPC中短码的一种有效构造方法,然而直接采用该算法构造的LDPC码的编码复杂度正比于码长的平方,这是其实用化过程中的一个瓶颈。针对这一问题,提出一种具有低编码复杂度和低错误平层的准循环扩展LDPC码的构造方法。该算法在PEG算法基础上,先构造出近似下三角结构的半随机基矩阵,然后再对基矩阵进行扩展,该方法可以在不改变基矩阵的度分布比例情况下,有效消除短环。仿真结果表明,所提出的方法构造的LDPC码比原始的PEG算法构造的随机LDPC码具有更低的错误平层,而且编码复杂度更低,更易于硬件实现。     

准规则Q矩阵LDPC码编码器设计

设计了一种准规则Q矩阵LDPC码编码器.该编码器基于准规则Q矩阵LDPC码的校验矩阵,其编码复杂度与信息位的长度成正比,有效降低了编码复杂度和设计难度.在Quartus Ⅱ平台上用FPGA实现了该编码器,结果证明其硬件资源占用很少.     

非规则LDPC码编码器的FPGA实现

文中硬件实现了一种非规则的低密度奇偶校验码在一定的约束条件下,利用具有一定结构的校验矩阵来降低编码复杂度的LDPC码,并给出了编码器设计实现原理、结构和基本组成。在Quartus 9.0软件平台上采用基于FPGA的Verilog硬件描述语言,在Altera的Cyclone系列型号为EP1C6Q240C8N的芯片硬件平台实现了整个编码过程中所有模块的功能,并通过Matlab验证了编码结果的正确性。同时,该编码方案还可灵活应用于不同码长的系统中。     

HIGH-PERFORMANCE SIMPLE-ENCODING GENERATOR-BASED SYSTEMATIC IRREGULAR LDPC CODES AND RESULTED PRODUCT CODES

Low-Density Parity-Check (LDPC) code is one of the most exciting topics among the coding theory community.It is of great importance in both theory and practical communications over noisy channels.The most advantage of LDPC codes is their relatively lower decoding complexity compared with turbo codes,while the disadvantage is its higher encoding complexity.In this paper,a new ap- proach is first proposed to construct high performance irregular systematic LDPC codes based on sparse generator matrix,which can significantly reduce the encoding complexity under the same de- coding complexity as that of regular or irregular LDPC codes defined by traditional sparse parity-check matrix.Then,the proposed generator-based systematic irregular LDPC codes are adopted as con- stituent block codes in rows and columns to design a new kind of product codes family,which also can be interpreted as irregular LDPC codes characterized by graph and thus decoded iteratively.Finally, the performance of the generator-based LDPC codes and the resultant product codes is investigated over an Additive White Gaussian Noise (AWGN) and also compared with the conventional LDPC codes under the same conditions of decoding complexity and channel noise.     

基于非规则LDPC码的图像传输性能

LDPC码性能非常逼近香农极限且实现复杂度低,具有很强的纠错抗干扰能力,几乎适用于所有信道。在此采用DVB-S2标准中LDPC码的构造和编码方案,重点研究了LDPC码的译码原理,并将其用于加性高斯白噪声信道（AWGN Channel）图像的传输中。仿真结果表明在非规则LDPC码在低信噪比情况下,能为图像传输带来显著性能提高,且系统复杂度低,译码时延短。     

一种可快速编码的QC-LDPC码构造新方法

为解决LDPC码的编码复杂度问题,使其更易于硬件实现,提出了一种可快速编码的准循环LDPC码构造方法。该方法以基于循环置换矩阵的准循环LDPC码为基础,通过适当的打孔和行置换操作,使构造码的校验矩阵具有准双对角线结构,可利用校验矩阵直接进行快速编码,有效降低了LDPC码的编码复杂度。仿真结果表明,与IEEE 802.16e中的LDPC码相比,新方法构造的LDPC码在低编码复杂度的基础上获得了更好的纠错性能。     

Efficient encoding of low-density parity-check codes

Low-density parity-check (LDPC) codes can be considered serious competitors to turbo codes in terms of performance and complexity and they are based on a similar philosophy: constrained random code ensembles and iterative decoding algorithms. We consider the encoding problem for LDPC codes. More generally we consider the encoding problem for codes specified by sparse parity-check matrices. We show how to exploit the sparseness of the parity-check matrix to obtain efficient encoders. For the (3,6)-regular LDPC code, for example, the complexity of encoding is essentially quadratic in the block length. However, we show that the associated coefficient can be made quite small, so that encoding codes even of length n≃100000 is still quite practical. More importantly, we show that “optimized” codes actually admit linear time encoding     

Bandwidth-Efficient Modulation Codes Based on Nonbinary Irregular Repeat–Accumulate Codes

Using nonbinary low-density parity-check (LDPC) codes with random-coset mapping, Bennatan and Burshtein constructed bandwidth-efficient modulation codes with remarkable performance under belief propagation (BP) decoding. However, due to the random nature of LDPC codes, most of the good LDPC codes found in the literature do not have a simple encoding structure. Thus, the encoding complexity of those LDPC codes can be as high as O(N ²), where N is the codeword length. To reduce the encoding complexity, in this paper, nonbinary irregular repeat-accumulate (IRA) codes with time-varying characteristic and random-coset mapping are proposed for bandwidth-efficient modulation schemes. The time-varying characteristic and random-coset mapping result in both permutation-invariance and symmetry properties, respectively, in the densities of decoder messages. The permutation-invariance and symmetry properties of the proposed codes enable the approximations of densities of decoder messages using Gaussian distributions. Under the Gaussian approximation, extrinsic information transfer (EXIT) charts for nonbinary IRA codes are developed and several codes of different spectral efficiencies are designed based on EXIT charts. In addition, by proper selection of nonuniform signal constellations, the constructed codes are inherently capable of obtaining shaping gains, even without separate shaping codes. Simulation results indicate that the proposed codes not only have simple encoding schemes, but also have remarkable performance that is even better than that constructed using nonbinary LDPC codes.     

低复杂度的LDPC码联合编译码构造方法研究

LDPC码因为其具有接近香农限的译码性能和适合高速译码的并行结构,已经成为纠错编码领域的研究热点。LDPC码校验矩阵的构造是基于稀疏的随机图,所以该类码字编码和译码的硬件实现比较复杂。以单位阵的循环移位阵为基本单元,构造LDPC码的校验矩阵,降低了LDPC码在和积算法下的译码复杂度。同时考虑到LDPC码的编码复杂度,给出了一种可以简化编码的结构。针对该方案构造的LDPC码,提出了消除其二分图上的短圈的方法。通过大量的仿真和计算分析,本文比较了这种LDPC码和随机构造的LDPC码在误码率性能,圈长分布以及最小码间距估计上的差异。     

Approximately Lower Triangular Ensembles of LDPC Codes With Linear Encoding Complexity

The complexity of brute-force encoding of low-density parity-check (LDPC) codes is proportional to the square value of the block length. Richardson and Urbanke have proposed efficient encoding algorithms for LDPC codes. These algorithms permute the parity-check matrix of the code iteratively, such that it becomes approximately lower triangular. We propose a new approach for efficient encoding of LDPC codes in which we modify the code ensemble to force an approximate lower triangular structure, thus eliminating the need to apply the algorithms of Richardson and Urbanke in this ensemble. We prove that the new ensemble has the same asymptotic threshold as the corresponding standard ensemble. The new ensemble can be used for linear time encoding of an arbitrary code profile. Computer simulations confirm that the performances of the standard and new ensembles are also very similar when using finite length codes     

多信源多中继编码协作系统准循环LDPC码的联合设计与性能分析

为解决多信源多中继低密度奇偶校验(LDPC)码编码协作系统编码复杂度高、编码时延长的问题,该文引入一种特殊结构的LDPC码—基于生成矩阵的准循环LDPC码(QC-LDPC)码。该类码结合了QC-LDPC码与基于生成矩阵LDPC (G-LDPC)码的特点,可直接实现完全并行编码,极大地降低了中继节点的编码时延及编码复杂度。在此基础上,推导出对应于信源节点和中继节点采用的QC-LDPC码的联合校验矩阵,并基于最大公约数(GCD)定理联合设计该矩阵以消除其所有围长为4, 6(girth-4, girth-6)的短环。理论分析和仿真结果表明,在同等条件下该系统的误码率(BER)性能优于相应的点对点系统。仿真结果还表明,与采用显式算法构造QC-LDPC码或一般构造QC-LDPC码的协作系统相比,采用联合设计QC-LDPC码的系统均可获得更高的编码增益。