基于翻转信息熵的组合逻辑电路功耗分析

基于信息熵的复杂度分析方法是在VLSI设计流程的高层次抽象阶段对组合逻辑电路功耗和面积进行分析估计的可行方法之一.本文通过提出新的利用翻转信息熵进行电路实现面积和功耗估计的理论方法,改善了面积和功耗估计精度.大量基于随机电路和BENCHMARK电路的实验结果表明,上述方法能够使面积和功耗估计的相对误差分别降低24.3% (从12.74%到9.65%)和15.4% (从13.67%到11.57%).     

一种基于忆阻器的可重配置逻辑电路

分析了具有阈值特性的双极性忆阻器模型的阈值电压和高低阻态开关特性,提出了一种基于该模型的可重配置逻辑电路。与基于忆阻器的蕴含逻辑门电路相比,可重配置逻辑电路具备逻辑运算的完备性,在实现“非”、“或”、“与”运算时,运算速度更快、功耗更低。仿真实验验证了电路逻辑功能的正确性,为设计运算速度更快、功耗更低的全加器和数选器等逻辑电路提供了参考。     

扫描位移过程中低功耗测试的设计与实现

针对扫描位移功耗过高带来的生产成本增加、良率降低的问题,提出采用时钟相位调整技术和逻辑阻隔技术相组合的方式来降低测试功耗。利用布局布线之后的时钟偏差和物理位置等信息对时钟相位进行调整,从而降低峰值功耗;通过寄存器输出端的扇出数量来决定阻隔逻辑电路插入点,从而降低平均功耗。将该方案应用于实际项目中,从面积、覆盖率、功耗角度分析了时钟相位调整技术和逻辑阻隔技术的特点。结果表明,在面积和覆盖率影响较小的情况下,采用两种技术组合后扫描位移的峰值功耗降低了73.24%,平均功耗降低了6.78%。该方案具有良好的实用性,可为大规模集成电路低功耗可测性设计提供参考。     

低成本BIST映射电路的设计与优化

低成本BIST利用映射电路对自测试线形反馈移位寄存器进行优化,将对故障覆盖率无贡献的测试向量屏蔽掉,有效提高了故障覆盖率,降低了测试功耗。映射电路的设计是低成本BIST设计的关键,为了降低其硬件开销和功耗、提高参数性能,该映射逻辑电路对测试向量的种子进行映射,并通过相容逻辑变量合并、布尔代数化简等方法对映射电路进行优化,有效地降低了测试应用时间、测试功耗和硬件开销。     

基于差分传输管预充电逻辑的功耗恒定性电路改进设计

通过分析差分传输管预充电逻辑(DP2L)的电路结构,发现该电路还无法达到完全的功耗恒定特性,仍然存在被功耗攻击的风险。针对该问题,该文对DP2L的电路结构进行改进,并用Hspice对改进前后的电路进行模拟仿真测试。实验表明:改进后的DP2L电路结构具有更好的功耗恒定特性,更能满足该逻辑电路的设计要求。     

基于差分传输管预充电逻辑的功耗恒定性电路改进设计

通过分析差分传输管预充电逻辑(DP2L)的电路结构,发现该电路还无法达到完全的功耗恒定特性,仍然存在被功耗攻击的风险.针对该问题,该文对DP2L的电路结构进行改进,并用Hspice对改进前后的电路进行模拟仿真测试.实验表明:改进后的DP2L电路结构具有更好的功耗恒定特性,更能满足该逻辑电路的设计要求.     

基于数字电视基带SoC芯片的可测性设计

介绍了基于数字电视基带SoC芯片的可测性设计方案.根据系统中不同模块的特点采取有针对性的可测性设计方案,对片内存储器进行内建自测试;对组合逻辑电路、时序逻辑电路采用近全扫描的测试方案;最后采用IEEE1149.1的控制单元作为芯片可测性设计部分的控制单元,控制芯片的测试功能.经测试,该可测性设计满足设计规划的面积和功耗的要求,并且系统的测试覆盖率达到了99.26%.     

抗功耗攻击的逻辑电路研究

通过分析双轨电路的主要功耗泄露类型,评估了传统抗功耗攻击逻辑电路的安全性,指出其安全性漏洞。针对其漏洞,对LBDL电路进行改进,并提出了一种将改进后的电路与掩码技术相结合的MLBDL电路。Hspice仿真实验表明,MLBDL电路不仅能够消除由双轨信号布线差异引起的功耗泄露,而且能够消除由输入延时差异引起的功耗泄露,其抗功耗攻击能力显著增强。     

基于RTD的新型全加器设计

单双稳态转换逻辑单元(MOBILE)是基于共振隧穿二极管(RTD)电路的一个重要逻辑单元,非常适合阈值逻辑电路设计。由MOBILE可以构成阈值逻辑门(TG)和广义阈值逻辑门(GTG)等阈值逻辑电路。本文通过将三变量异或函数转化为较简单、理想的GTG输入输出函数形式,设计了由GTG构成的新型三变量异或门,并利用该三变量异或门设计了新型的全加器。通过HSPICE仿真和性能比较,该全加器不仅器件数量少,输出延时短,而且能达到较高的工作频率、更小的电路功耗与功耗-延迟积。     

CMOS时序逻辑电路功耗估计的一种新方法

MOS时序逻辑电路由于存在时序反馈环，使功耗分析变得相当复杂。文章提出了一种采用电路化简加速功耗估计的方法。对ISCAS’89和ISCAS’93基本测试电路的实验结果表明，此方法具有较好的计算精度和较短的计算时间。     

Robust subthreshold logic for ultra-low power operation

Digital subthreshold logic circuits can be used for applications in the ultra-low power end of the design spectrum, where performance is of secondary importance. In this paper, we propose two different subthreshold logic families: 1) variable threshold voltage subthreshold CMOS (VT-Sub-CMOS) and 2) subthreshold dynamic threshold voltage MOS (Sub-DTMOS) logic. Both logic families have comparable power consumption as regular subthreshold CMOS logic (which is up to six orders of magnitude lower than that of normal strong inversion circuit) with superior robustness and tolerance to process and temperature variations than that of regular subthreshold CMOS logic     

Sleep switch dual threshold voltage domino logic with reduced subthreshold and gate oxide leakage current

A circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. PMOS-only sleep transistors and a dual threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. Sleep transistors are added to the dynamic nodes in order to reduce the subthreshold leakage current by strongly turning off all of the high threshold voltage transistors. Similarly, the sleep switches added to the output nodes suppress the voltages across the gate insulating layers of the transistors in the fan-out gates, thereby minimizing the gate tunneling current. The proposed circuit technique lowers the total leakage power by 88 to 97% as compared to the standard dual threshold voltage domino logic circuits. Similarly, a 22 to 44% reduction in the total leakage power is observed as compared to a previously published sleep switch scheme in a 45 nm CMOS technology.     

PMOS-Only Sleep Switch Dual-Threshold Voltage Domino Logic in Sub-65-nm CMOS Technologies

A circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. Only p-channel sleep transistors and a dual-threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. Sleep transistors are added to the dynamic nodes in order to reduce the subthreshold leakage current by strongly turning off all of the high-threshold voltage transistors. Similarly, the sleep switches added to the output nodes suppress the voltages across the gate insulating layers of the transistors in the fan-out gates, thereby minimizing the gate tunneling current. The proposed circuit technique lowers the total leakage power by up to 77% and 97% as compared to the standard dual-threshold voltage domino logic circuits at the high and low die temperatures, respectively. Similarly, a 22% to 44% reduction in the total leakage power is observed as compared to a previously published sleep switch scheme in a 45-nm CMOS technology. The energy overhead of the circuit technique is low, justifying the activation of the proposed sleep scheme by providing a net savings in total energy consumption during short idle periods.     

Sleep switch dual threshold Voltage domino logic with reduced standby leakage current

A circuit technique is presented for reducing the subthreshold leakage energy consumption of domino logic circuits. Sleep switch transistors are proposed to place an idle dual threshold voltage domino logic circuit into a low leakage state. The circuit technique enhances the effectiveness of a dual threshold voltage CMOS technology to reduce the subthreshold leakage current by strongly turning off all of the high threshold voltage transistors. The sleep switch circuit technique significantly reduces the subthreshold leakage energy as compared to both standard low-threshold voltage and dual threshold voltage domino logic circuits. A domino adder enters and leaves a low leakage sleep mode within a single clock cycle. The energy overhead of the circuit technique is low, justifying the activation of the proposed sleep scheme by providing a net savings in total power consumption during short idle periods.     

Leakage Power Characteristics of Dynamic Circuits in Nanometer CMOS Technologies

Temperature-dependent subthreshold and gate-oxide leakage power characteristics of domino logic circuits under the influence of process parameter variations are evaluated in this paper. Preferred input vectors and node voltage states that minimize the total leakage power consumption are identified at the lower and upper extremes of a typical die temperature spectrum. New low-leakage circuit design guidelines are presented based on the results. Significantly increased gate dielectric tunneling current, as described in this paper, dramatically changes the leakage power characteristics of dynamic circuits in deeply scaled nanometer CMOS technologies. Contrary to the previously published techniques, a charged dynamic-node voltage state with low inputs is preferred for reducing the total leakage power consumption in the most widely used types of single- and dual-threshold voltage domino gates, particularly at low die temperatures. Furthermore, leakage power savings provided by the dual-threshold voltage domino logic circuit techniques based on input gating are all together reduced due to the significance of gate dielectric tunneling in sub-45-nm CMOS technologies.     

Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications

This paper presents a novel approach for implementing ultra-low-power digital components and systems using source-coupled logic (SCL) circuit topology, operating in weak inversion (subthreshold) regime. Minimum size pMOS transistors with shorted drain-substrate contacts are used as gate-controlled, very high resistivity load devices. Based on the proposed approach, the power consumption and the operation frequency of logic circuits can be scaled down linearly by changing the tail bias current of SCL gates over a very wide range spanning several orders of magnitude, which is not achievable in subthreshold CMOS circuits. Measurements in conventional 0.18 m CMOS technology show that the tail bias current of each gate can be set as low as 10 pA, with a supply voltage of 300 mV, resulting in a power-delay product of less than 1 fJ. Fundamental circuits such as ring oscillators and frequency dividers, as well as more complex digital blocks such as parallel multipliers designed by using the STSCL topology have been experimentally characterized.     

Leakage Current Reduction Using Subthreshold Source-Coupled Logic

The performance of subthreshold source-coupled logic (STSCL) circuits for ultra-low-power applications is explored. It is shown that the power consumption of STSCL circuits can be reduced well below the subthreshold leakage current of static CMOS circuits. STSCL circuits exhibit a better power–delay performance compared with their static CMOS counterparts in situations where the leakage current constitutes a significant part of the power dissipation of static CMOS gates. The superior control on power consumption, in addition to the lower sensitivity to the process and supply voltage variations, makes the STSCL topology very suitable for implementing ultra-low-power low-frequency digital systems in modern nanometer-scale technologies. An analytical approach for comparing the power–delay performance of these two topologies is proposed.      

A minimum total power methodology for projecting limits on CMOS GSI

A circuit design methodology minimizing total power drain of a static complementary metal-oxide-semiconductor (CMOS) random logic network for a prescribed performance, operating temperature range, and short channel threshold voltage rolloff is investigated. Physical, continuous, smooth, and compact “transregional” MOSFET drain current models that consider high-field effects in scaled devices and permit tradeoffs between saturation drive current and subthreshold leakage current are employed to model CMOS circuit performance and power dissipation at low voltages. Transregional models are used in conjunction with physical short channel MOSFET threshold voltage rolloff models and stochastic interconnect distributions to project optimal supply voltages, threshold voltages, and device channel widths minimizing total power dissipated by CMOS logic circuits for each National Technology Roadmap for Semiconductors (NTRS) technology generation. Optimum supply voltage, corresponding to minimum total power dissipation, is projected to scale to 510 mV for the 50-nm 10-GHz CMOS generation in the year 2012. Techniques exploiting datapath parallelism to further scale the supply voltage are shown to offer decreasing reductions in power dissipation with technology scaling     

Leakage Biased pMOS Sleep Switch Dynamic Circuits

In this brief, a low-overhead circuit technique is proposed to simultaneously reduce subthreshold and gate-oxide leakage currents in domino logic circuits. pMOS sleep transistors and a dual threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. A sleep transistor added to the dynamic node strongly turns off all of the high threshold voltage transistors. Similarly, a sleep switch added to the output inverter exploits the initially high subthreshold and gate-oxide leakage currents for placing a circuit into an ultimately low leakage state. The proposed circuit technique lowers the total leakage power by 56.1% to 97.6% as compared to standard dual threshold voltage domino logic circuits. Similarly, a 4.6% to 50.6% reduction in total leakage power is observed as compared to a previously published sleep switch scheme in a 45-nm CMOS technology     

一种低功耗的锂离子电池保护电路的设计

设计了一种适用于CMOS工艺的锂离子电池充放电保护电路,采用工作在亚阈值区的电路结构,使电路具有超低消耗电流驱动、高精度检测电压等特点。通过取样电路、基准电路和偏置电路设计的改进,保护电路功耗较低并且在较低电压下可以正常工作。模拟结果表明,该电路实现了基本的电池保护功能并在功耗方面达到了设计的目标。