All-optical switching based on self-assembled halide perovskite microwires

Optical switching is a fundamental element in all-optical integrated circuits and networks with ultrahigh speed and low energy consumption compared to their electronic counterparts.Switching on/off the waveguiding with another light beam demands large optical nonlinearity to compactify device footprint and decrease energy consumption,which is difficult to achieve in photonic systems.     

Message from the Guest Editor for the Special Issue

The communications industry and research have been developed greatly since optical fiber communications technologies became practical. More than 80 percent of the traffic of today＇s communications network, which increases at the speed more than Moore＇s law attributed to the rapidly growing network users and services, is carried by optical fiber networks. Optical fiber communications networks will play an essential role in the development of information society in the future for its large capacity, high bit rate, low energy consumption and low cost. Moreover, the business Terabit/s transsport systems and Petabit/s switching nodes must be implemented by optical communications technologies. In a word, optical fiber communications technologies will be the key part of next generation network in China.     

PERFORMANCE ANALYSIS FOR ATM SWITCHING OF MIXED CONTINUOUS-BIT-RATE AND BURSTY TRAFFIC WITH SMOOTHING FUNCTION

Traditional packet switching networks have typically employed window-based congestion control schemes in order to regulate traffic flow. In ATM networks, the high speed of the communication links and the varied nature of the carried traffic make such schemes inappropriate. Therefore, simpler and more efficient schemes have to be proposed to improve the congestion control for ATM switching. This paper presents an exact performance analysis of ATM switching whose inputs consist of Continuous-Bit-Rate(CBR) and bursty traffic. The CBR traffic and bursty traffic are described by Bernoulli process and the Interrupted Bernoulli Process(IBP), respectively. Bursty traffic smoothing mechanism is analyzed. With the use of a recursive algorithm, the cell loss probability and the average delay for ATM switching of mixed CBR and bursty traffic are exactly calculated. Traffic smoothing could be implemented at a slower peak rate keeping the average rate constant or decreasing the average bursty length. Both numerical a     

Spectral resource defragmentation based on PCE in flexible bandwidth optical networks

The granularity of the flexible bandwidth optical network is the spectral slots,which is much smaller than that of the wavelength switch optical network.For the dynamic clients’ connections setup and tear down processes,it will give rise to fragmentation of spectral resources.It is the decline in the probability of finding sufficient contiguous spectrum for new connections that result in the fragmentation of spectral resource.To be more specific,these spectra may be unavailable and waste.In this case,the severe waste of the spectrum will lead to low efficiency in spectral utilization and will not adapt to large capacity requirements of transmission in the future.Because path computation element(PCE) framework has the characteristics of the central disposal and deployment of the spectrum resource,we construct the spectral resource allocation scenario based on PCE framework in the flexible bandwidth optical network to use spectrum resource effectively.Based on the principle of the generation of the fragmentation,we put forward a spectrum resource defragmentation algorithm to consolidate the available spectrum for clients’ connections.The simulation results indicate that this algorithm is able to reduce fragmentation of network,improve the continuity of spectral resource,reduce the blocking rate of services in the network and improve the spectral efficiency significantly.     

Virtual Network Embedding Algorithm for Load Balance with Various Requests

Virtual network embedding （VNE） is a crucial technology for network virtualization to allocate network resource. Virtual network request in which node and link resource have great disparity will lead to unbal- anced resource distribution and lower acceptance ratio of virtual network requests. In this paper, we provide a vir- tual network embedding algorithm for load balance with various requests. It maps virtual nodes to substrate nodes of which node link residual resource ratio is closest to that of virtual nodes, and then maps the virtual link to physical path using shortest path first algorithm with the link node residual resource ratio constraint. Simulation shows that the provided algorithm can get higher acceptance ratio and network resource utilization for load balance.     

一种源节点进行时隙疏导的光突发网状网络(英文)

In this paper, we propose an optical burst network architecture supporting the generic mesh topology. The intermediate node architecture of the mesh network can be the same with current wavelength switching Wave-length Division Multiplexing (WDM) networks, and thus can reuse existing deployed infrastructure. We employ a novel Optical Time Slot Interchange (OTSI) at the source nodes for the first time to mitigate the burst contention and to increase the bandwidth utilization. Time and wavelength-domain reuse in the OTSI significantly saves optical components and reduces blocking probability.     

Adaptability Analysis of Fluctuating Traffic for IP Switching and Optical Switching

The technological development of smart devices and Internet of Things(IoT)has brought ever-larger bandwidth and fluctuating traffic to existing networks.The analy?sis of network capital expenditure(CAPEX)is extremely important and plays a fundamen?tal role in further network optimizing.In this paper,an adaptability analysis is raised for IP switching and optical transport network(OTN)switching in CAPEX when the service bandwidth is fluctuating violently.This paper establishes a multi-layer network architec?ture through Clos network model and discusses impacts of maximum allowable blocking rate and service bandwidth standard deviation on CAPEX of IP network and OTN network to find CAPEX demarcation point in different situations.As simulation results show,when the bandwidth deviation mean rate is 0.3 and the maximum allowable blocking rate is 0.01,the hardware cost of OTN switching will exceed IP switching as the average band?width is greater than 6100 Mbit/s.When the service bandwidth fluctuation is severe,the hardware cost of OTN switching will increase and exceed IP switching as the single port rate is allowed in optical switching.The increasing of maximum allowable blocking rate can decrease hardware cost of OTN switching.Finally,it is found that Flex Ethernet(FlexE)can be used to decrease CAPEX of OTN switching greatly at this time.     

Blockchain-based collaborative edge caching scheme fortrustworthy content sharing

Moving data from cloud to the edge network can effectively reduce traffic burden on the core network, and edge collaboration can further improve the edge caching capacity and the quality of service ( QoS). However, it is difficult for various edge caching devices to cooperate due to the lack of trust and the existence of malicious nodes. In this paper,blockchain which has the distributed and immutable characteristics is utilized to build a trustworthy collaborative edge caching scheme to make full use of the storage resources of various edge devices. The collaboration process is described in this paper, and a proof of credit (PoC) protocol is proposed, in which credit and tokens are used to encourage nodes to cache and transmit more content in honest behavior. Untrusted nodes will pay for their malicious actions such as tampering or deleting cached data. Since each node chooses strategy independently to maximize its benefits in an environment of mutual influence, a non-cooperative game model is designed to study the caching behavior among edge nodes. The existence of Nash equilibrium (NE) is proved in this game, so the edge server (ES) can choose the optimal caching strategy for all collaborative devices, including itself, to obtain the maximum rewards. Simulation results show that the system can save mining overhead as well as organize a trusted collaborative edge caching effectively.     

UNITED STABILIZING SCHEME FOR EDGE DELAY IN OPTICAL BURST SWITCHED NETWORKS

A novel scheme, namely united stabilizing scheme for edge delay, is introduced in optical burst switched networks. In the scheme, the limits of burst length and assembly time are both set according to certain qualifications. For executing the scheme, the conception for unit input bit rate is introduced to improve universality, and the assembly algorithm with a buffer safety space under the self-similar traffic model at each ingress edge router is proposed. Then, the components of burst and packet delay are concluded, and the equations that limits of burst length and assembly time should satisfy to stabilize the burst edge delay under different buffer offered loads are educed. The simulation results show that united stabilizing scheme stabilizes both burst and packet edge delay to a great extent when buffer offered load changes from 0.1 to 1, and the edge delay of burst and packet are near the limit values under larger offered load, respectively.     

A burst segmentation-deflection routing contention resolution mechanism in OBS networks

One of the key problems to hinder the realization of optical burst switching(OBS) technology in the core networks is the losses due to the contention among the bursts at the core nodes.Burst segmentation is an effective contention resolution technique used to reduce the number of packets lost due to the burst losses.In our work,a burst segmentation-deflection routing contention resolution mechanism in OBS networks is proposed.When the contention occurs,the bursts are segmented according to the lowest packet loss probability of networks firstly,and then the segmented burst is deflected on the optimum routing.An analytical model is proposed to evaluate the contention resolution mechanism.Simulation results show that high-priority bursts have significantly lower packet loss probability and transmission delay than the low-priority.And the performance of the burst lengths,in which the number of segments per burst distributes geometrically,is more effective than that of the deterministically distributed burst lengths.     

Ranking Potential Reply-Providers in Community Question Answering System

Community Question Answering （CQA） websites have greatly facilitated users＇ lives, with an increasing number of people seeking help and exchanging ideas on the Internet. This newlymerged community features two characteristics： social relations and an ask-reply mechanism. As users＇ behaviours and social statuses play a more important role in CQA services than traditional answer retrieving websites, researchers＇ concerns have shifted from the need to passively find existing answers to actively seeking potential reply providers that may give answers in the near future. We analyse datasets derived from an online CQA system named ＂Quora＂, and observed that compared with traditional question answering services, users tend to contribute replies rather than questions for help in the CQA system. Inspired by the findings, we seek ways to evaluate the users＇ ability to offer prompt and reliable help, taking into account activity, authority and social reputation char- acteristics. We propose a hybrid method that is based on a Question-User network and social network using optimised PageRank algorithm. Experimental results show the efficiency of the proposed method for ranking potential answer-providers.     

一种应用于GNSS接收机的低噪声和低杂散频率综合器

A low phase noise and low spur phase locked loop （PLL） frequency synthesizer for use in global navigation satellite system （GNSS） receivers is proposed. To get a low spur, the symmetrical structure of the phase frequency detector （PFD） produces four control signals, which can reach the charge pump （CP） simultaneously, and an improved CP is realized to minimize the charge sharing and the charge injection and make the current matched. Additionally, the delay is controllable owing to the programmable PFD, so the dead zone of the CP can be eliminated. The output frequency of the VCO can be adjusted continuously and precisely by using a programmable LC-TANK. The phase noise of the VCO is lowered by using appropriate MOS sizes. The proposed PLL frequency synthesizer is fabricated in a 0.18 μm mixed-signal CMOS process. The measured phase noise at 1 MHz offset from the center frequency is -127.65 dBc/Hz and the reference spur is -73.58 dBc.     

一个全差分可编程的多通道神经信号记录芯片

A multi-channel,fully differential programmable chip for neural recording application is presented.The integrated circuit incorporates eight neural recording amplifiers with tunable bandwidth and gain,eight 4thorder Bessel switch capacitor filters,an 8-to-1 analog time-division multiplexer,a fully differential successive approximation register analog-to-digital converter(SAR ADC),and a serial peripheral interface for communication.The neural recording amplifier presents a programmable gain from 53 dB to 68 dB,a tunable low cut-off frequency from 0.1 Hz to 300 Hz,and 3.77 μVrms input-referred noise over a 5 kHz bandwidth.The SAR ADC digitizes signals at maximum sampling rate of 20 kS/s per channel and achieves an ENOB of 7.4.The integrated circuit is designed and fabricated in 0.18-μm CMOS mix-signal process.We successfully performed a multi-channel in-vivo recording experiment from a rat cortex using the neural recording chip.     

A power-efficient 12-bit analog-to-digital converter with a novel constant-resistance CMOS input sampling switch

Apower-efficient 12-bit40-MS/spipelineanalog-to-digitalconverter（ADC）implementedina0.13 μm CMOS technology is presented. A novel CMOS bootstrapping switch, which offers a constant on-resistance over the entire input signal range, is used at the sample-and-hold front-end to enhance the dynamic performance of the pipelined ADC. By implementing with 2.5-bit-per-stage and a simplified amplifier sharing architecture between two successive pipeline stages, a very competitive power consumption and small die area can be achieved. Meanwhile, the substrate-biasing-effect attenuated T-type switches are introduced to reduce the crosstalk between the two op- amp sharing successive stages. Moreover, a two-stage gain boosted recycling folded cascode （RFC） amplifier with hybrid frequency compensation is developed to further reduce the power consumption and maintain the ADC＇s performance simultaneously. The measured results imply that the ADC achieves a spurious-free dynamic range （SFDR） of 75.7 dB and a signal-to-noise-plus-distortion ratio （SNDR） of 62.74 dB with a 4.3 MHz input signal; the SNDR maintains over 58.25 dB for input signals up to 19.3MHz. The measured differential nonlinearity （DNL） and integral nonlinearity （INL） are -0.43 to ＋0.48 LSB and -1.62 to ＋ 1.89 LSB respectively. The prototype ADC consumes 28.4 mW under a 1.2-V nominal power supply and 40 MHz sampling rate, transferring to a figure- of-merit （FOM） of 0.63 pJ per conversion-step.     

一种基于低中频接收相位选择发射结构的工作在2.4GHz面向WPAN应用的超低功耗收发机

This paper presents a 2.4 GHz CMOS transceiver for the wireless personal area network （WPAN） inte- grated in 0.18/zm CMOS technology. This transceiver adopts a low-IF receiver, a MUX based transmitter and a fast-setting fractional-N frequency synthesizer. For achieving low cost and low power consumption, an inductor- less receiver front-end, an adaptive analog baseband, a low power MUX and a current-reused phase-locked loop （PLL） have been proposed in this work. Measured results show that the receiver achieves-8 dBrn of lIP3 and 31 dB of image rejection. The transmitter delivers 0 dBm output power at a data rate of 2 Mbps. The current consumption is 7.2 mA in the receiving mode and 6.9 mA in the transmitting mode, respectively.     

Low power high gain gain-controlled LNA and mixer for GNSS receivers Wei Binbin(魏斌斌)1, Jiang Jinguang(江金光)1,2,3*

A low power high gain gain-controlled LNA ＋ mixer for GNSS receivers is reported. The high gain LNA is realized with a current source load. Its gain-controlled ability is achieved using a programmable bias circuit. Taking advantage of the high gain LNA, a high noise figure passive mixer is adopted. With the passive mixer, low power consumption and high voltage gain of the LNA ＋ mixer are achieved. To fully investigate the performance of this circuit, comparisons between a conventional LNA ＋ mixer, a previous low power LNA ＋ mixer, and the proposed LNA ＋ mixer are presented. The circuit is implemented in 0.18 #m mixed-signal CMOS technology. A 3.8 dB noise figure, an overall 45 dB converge gain and a 10 dB controlled gain range of the two stages are measured. The chip occupies 0.24 mm2 and consumes 2 mA current under 1.8 V supply.     

用于无采保流水线ADC的高速低功耗低失调动态比较器

A novel fully differential high speed high resolution low offset CMOS dynamic comparator has been implemented in the SMIC 0.18 μm process used for a sample-and-hold amplifier （SHA）-less pipelined analog-to-digital converters （ADC）. Based on the analysis and optimization between delay time and offset, an enhanced reset architecture with transmission gate was introduced to speed up the comparison and reset procedure. Four inputs with two cross coupled differential pairs, reconstituted bias circuit for tail current transistor and common centroid layouts make the comparator more robust against mismatch and process variations. The simulation results demonstrate that the proposed design achieves 1 mV sensitivity at 2.2 GHz sampling rate with a power consumption of 510 μW, while the mean offset voltage is equal to 10.244 mV.     

一种应用于GPS接收机的高线性度SiGe HBT低噪声放大器

A high linearity 1.575 GHz SiGe：HBT low noise amplifier （LNA） for global positioning system applications is described. The bipolar cascoded with an MOSFET LNA was fabricated in a commercial 0.18 μm SiGe BiCMOS process, A resistor bias feed circuit with a feedback resistor was designed for the LNA input transistor to improve its intermodulation and compression performance. The packaged chip tested on board has displayed a noise figure of 1. I 1 dB, a power gain of 18 dB, an output 1 dB compression point of ＋7.8 dBm and an input third-order intercept point of ＋1.8 dBm. The chip occupies a 500 × 560μm^2 area and consumes 3.6 mA from a 2.85 V power supply.     

一种应用于无线局域网具有3.01-3.82 GHz频率范围和6.29%调谐增益变化的CMOS LC压控振荡器

A wideband low-phase-noise LC voltage-controlled oscillator （VCO） with low VCO gain （Kvco） vari- ation for WLAN fractional-N frequency synthesizer application is proposed and designed on a 0.13-μm CMOS process. In order to achieve a low Kvco variation, an extra switched varactor array was added to the LC tank with the conventional switched capacitor array. Based on the proposed switched varactor array compensation technique, the measured Kvco is 43 MHz/V with only 6.29% variation across the entire tuning range. The proposed VCO provides a tuning range of 23.7% from 3.01 to 3.82 GHz, while consuming 9 mA of quiescent current from a 2.3 V supply. The VCO shows a low phase noise of-121.94 dBc/Hz at 1 MHz offset, from the 3.6 GHz carrier.