一种应用于能量攫取系统的低功耗的工作于亚阈值区域的基准电压源的设计

We propose a bandgap reference, which works in sub-threshold regions to the reduce power consumption in applications such as those in energy harvesting systems that stimulate the development of power management for low power consumption applications.Measurements shows that the supply current of the proposed bandgap reference is only 6.87 μA, including a voltage buffer consuming 3.6 μA of supply current, when the supply voltage is 5 V.The supply voltage can vary from 3 to 11 V and the line regulation of the proposed bandgap reference output voltage is 0.875 mV/V at room temperature.The temperature coefficiency is 88.9 ppm from 10 to 100° C when the supply voltage is 5 V.     

一种新颖的片内高压转低压电源转换方案

A novel power supply transform technique for high voltage IC based on the TSMC 0.6μm BCD process is achieved. An adjustable bandgap voltage reference is presented which is different from the traditional power supply transform technique. It can be used as an internal power supply for high voltage IC by using the push-pull output stage to enhance its load capability. High-order temperature compensated circuit is designed to ensure the precision of the reference. Only 0.01 mm^2 area is occupied using this novel power supply technique. Compared with traditional technique, 50% of the area is saved, 40% quiescent power loss is decreased, and the temperature coefficient of the reference is only 4.48 ppm/℃. Compared with the traditional LDO （low dropout） regulator, this power conversion architecture does not need external output capacitance and decreases the chip-pin and external components, so the PCB area and design cost are also decreased. The testing results show that this circuit works well.     

A sub-1 V high-precision CMOS bandgap voltage reference

A third-order, sub-1 V bandgap voltage reference design for low-power supply, high-precision applications is presented. This design uses a current-mode compensation technique and temperature-dependent resistor ratio to obtain high-order curvature compensation. The circuit was designed and fabricated by SMIC 0.18 μm CMOS technology. It produces an output reference of 713.6 mV. The temperature coefficient is 3.235 ppm/℃ in the temperature range of -40 to 120 ℃, with a line regulation of 0.199 mV/V when the supply voltage varies from 0.95 to 3 V. The average current consumption of the whole circuit is 49 μA at the supply voltage of 1 V.     

多管组合曲率补偿低压带隙基准源

A new bandgap reference(BGR) curvature compensation technology is proposed,which is a kind of multiple transistor combination.On the basis of the existing first-order bandgap reference technology,a compensation current circuit consisting of a sink current branch and a source current branch is added.The BGR was designed and simulated by using Semiconductor Manufacturing International Corporation(SMIC) 0.18μm CMOS process.The simulation results showed that when the power supply voltage was 1 V,the temperature coefficient of the BGR was 2.08 ppm/℃with the temperature range from—40 to 125℃,the power supply rejection ratio (PSRR) was—64.77 dB and the linear regulation was 0.44 mV/V with the supply power changing from 0.85 to 1.8 V.     

一种连续输出的小失调开关电容带隙基准源

An improved switched-capacitor bandgap reference with a continuous output voltage of 1.26 V has been implemented with Chartered 0.35-μm 5-V CMOS process. The output offset voltage, induced by non-ideal characteristics of operational amplifier and bias current generator, is suppressed by the proposed sample-and-hold circuit and self-bias technique. Experimental results show that the proposed circuit operates properly under a supply voltage varying from 3 to 5 V. The measured temperature coefficient is 112 ppm/℃ and the power supply rejection ratio of output voltage without any filtering capacitor is -40 dB and -33 dB at 100 Hz and 10 MHz, respectively.     

New Curvature-Compensated CMOS Bandgap Voltage Reference

A novel curvature-compensated CMOS bandgap voltage reference is presented. The reference utilizes two first order temperature compensations generated from the nonlinearity of the finite current gain β of vertical pnp bipolar transistor. The proposed circuit, designed in a standard 0.18 μm CMOS process, achieves a good temperature coefficient of 2.44 ppm/℃ with temperature range from --40℃ to 85 ℃, and about 4 mV supply voltage variation in the range from 1.4 V to 2.4 V. With a 1.8 V supply voltage, the power supply rejection ratio is -56dB at 10MHz.     

A high precision high PSRR bandgap reference with thermal hysteresis protection

To meet the accuracy requirement for the bandgap voltage reference by the increasing data conversion precision of integrated circuits,a high-order curvature-compensated bandgap voltage reference is presented employing the characteristic of bipolar transistor current gain exponentially changing with temperature variations.In addition,an over-temperature protection circuit with a thermal hysteresis function to prevent thermal oscillation is proposed.Based on the CSMC 0.5μm 20 V BCD process,the designed cir...     

A 150-nA 13.4-ppm/℃switched-capacitor CMOS sub-bandgap voltage reference

A nanopower switched-capacitor CMOS sub-bandgap voltage reference has been implemented using a Chartered 035-μm 3.3-V/5-V dual gate mixed-signal CMOS process.The proposed circuit generates a precise sub-bandgap voltage of 1 V.The temperature coefficient of the output voltage is 13.4 ppm/℃with the temperature varying from -20 to 80℃.The proposed circuit operates properly with the supply voltage down to 1.3 V,and consumes 150 nA at room temperature.The line regulation is 0.27%/V.The power supply rejection ratio at 100 Hz and 1 MHz is -39 dB and -51 dB,respectively.The chip area is 0.2 mm~2.     

An inherent curvature-compensated voltage reference using non-linearity of gate coupling coefficient

A novel current-mode voltage reference circuit which is capable of generating sub-1 V output voltage is presented. The proposed architecture exhibits the inherent curvature compensation ability. The curvature compensation is achieved by utilizing the non-linear behavior of gate coupling coefficient to compensate non-linear temperature dependence of base-emitter voltage. We have also utilized the developments in CMOS process to reduce power and area consumption. The proposed voltage reference is analyzed theoretically and compared with other existing methods. The circuit is designed and simulated in 180 nm mixed-mode CMOS UMC technology which gives a reference level of 246 mV. The minimum required supply voltage is 1 V with maximum current drawn of 9.24 μA. A temperature coefficient of 9 ppm/℃ is achieved over -25 to 125 ℃ temperature range. The reference voltage varies by ±11 mV across process corners. The reference circuit shows the line sensitivity of 0.9 mV/V with area consumption of 100 × 110 μm².     

闭环曲率补偿的低电源电压带隙基准源

A new low-voltage CMOS bandgap reference （BGR） that achieves high temperature stability is proposed. It feeds back the output voltage to the curvature compensation circuit that constitutes a closed loop circuit to cancel the logarithmic term of voltage VBE. Meanwhile a low voltage amplifier with the 0.5 μm low threshold technology is designed for the BGR. A high temperature stability BGR circuit is fabricated in the CSMC 0.5μm CMOS technology. The measured result shows that the BGR can operate down to 1 V, while the temperature coefficient and line regulation are only 9 ppm/℃ and 1.2 mV/V, respectively.     

一种高效的大功率宽带整流电路

提出了一种由π型匹配枝节、整流二极管、直通滤波器组成的高效大功率宽带整流电路。采用2只HSMS-282P肖特基二极管桥设计单级倍压整流电路,使电路在整流效率不下降的情况下提升输入的功率容量;采用π型匹配枝节实现阻抗匹配,使电路具有宽频特性,同时其并联短路枝节可以作为输入滤波器,实现小型化和整流效率的提高。直通滤波器用于抑制基频和二极管非线性产生的高次谐波,以提高整流效率。实测结果表示：在2.05~2.6 GHz带宽内整流效率大于60%;在2.45 GHz工作频率和35 dBm输入功率下,整流电路在330 Ω负载上获得70%的整流效率。该整流电路具有整流效率高、功率容量大、频带宽的特性,可为工程人员设计大功率微波整流电路提供设计指导。     

新型高性能的高频信号发生器

介绍一种性能优良的高频信号发生器,对其产生信号的频率、占空比等技术指标进行了分析讨论,给出了它在电子技术中相应的典型应用实例,它产生的信号波形清晰、频率、相位和幅度稳定,失真度低,性价比高,具有较高的实用价值。     

一种用于大功率音频功放的高稳定性LDO

设计了一种用于大功率音频功放的高稳定性低压差线性稳压器(LDO),对其电路结构和工作原理进行了分析,重点讨论了上电预充模块、环路稳定性及电源抑制能力。采用0.18μm 1P4M BCDMOS工艺,不同工艺角下,Cadence Spectre仿真表明,LDO的温度系数小于47.45 ppm/℃,瞬态响应最大变化量为50 mV,电源抑制大于71 dB@1 kHz,工作电压范围5 V~24 V,输出电压值为3.3 V;tt(渡越时间)模型下,工作电压为18 V 时,对大功率音频功放进行系统仿真,LDO 表现出约为30μs的启动时间,其输出电压值能很好地跟踪负载电流的变化。     

一种高集成高空间分辨率220 GHz检波器

本文设计了一种高集成检波器,其包含贴片天线、匹配电路、肖特基二极管和透镜。在中芯国际130nm工艺下将天线、匹配电路、肖特基二极管集成到一个芯片上,检波器的集成度相比于分离式有了明显的提高。为增强片上天线的方向性,进行了带有空气腔的尼龙透镜的设计和优化。透镜上的空气腔不但提供了组装空间而且减小了透镜体积。通过测试,天线在220 GHz辐射增益为22 dB,其中透镜贡献约为20dB。检波器测试得到的响应率可达到130-150V/W,对应的等效噪声功率（NEP）估算为400-460 。     

A high performances CMOS CCII and high frequency applications

In this paper, we propose an improved translinear based CCII configuration. Heuristic algorithm is used for optimal sizing regarding static and dynamic performances. PSPICE simulations for AMS 0.35 μm CMOS technology show that the current and voltage bandwidths are respectively 2.6 GHz and 3.9 GHz, and the parasitic resistance at port X (R _X ) has a value of 18 Ω for a control current of 100 μA. The improved configuration is used as a building block into high frequency design applications: a current controlled oscillator and a tunable fully integrable band pass filter. The oscillator frequency can be tuned in the range of [290–475 MHz] by a simple variation of a DC current. The central frequency of the band pass filter can be varied in the range of [1.22–1.56 GHz] and the quality factor vary in the range [8–306] with a simple variation of a DC current.     

Pseudospark switches for high repetition rates and high currentapplications

The state-of-the-art of pseudospark switch (PSS) development is reported. In addition to the replacement of thyratrons for high power applications in TE-gas-discharge lasers, PSSs have been tested at high repetition rates up to 2 kHz. In order to minimize the erosion rate and to reduce total switch inductance, multichannel PSSs with various geometrical configurations have been investigated: linear, coaxial, and radial arrangements of the parallel discharge channels. All three configurations possess distinct advantages in pulsed power technology, i.e. linear systems fit well into striplines. Beyond this, PSSs gain increasing importance in high current devices like fast pinches, plasma foci, or powerful modulators, i.e. for magnetoforming. A single-channel switch for hold-off voltages up to 30 kV at peak currents of ≈100 kA has been tested for a damped sinusoidal pulse of a 5 μs duration at a repetition rate of up to 0.2 Hz, with and without electrode cooling     

New high power, high performance power converter systems

A new, high performance, low cost power converter system architecture is proposed. The system consists of a main converter and a multifunctional load conditioner. The main converter deals with most of the power flow running at a low switching frequency. The load conditioner is designed at a much lower power level running at a high-switching frequency. The load conditioner can (1) act like a current source and inject harmonic currents required by the load; (2) act like an active resistor to provide damping to the main converter; and (3) for three-phase inverters, decouple the coupling sources in the main inverter model in the rotating coordinates to make the control loop design for the main inverter much easier. The concept has been proved by simulation and experimental results on a 150 kW high performance three-phase utility power supply prototype. The proposed system configuration can be used in high power DC-DC converters, inverters, PFC and UPS applications     

高度集成、功能丰富的32位MCU满足了消费电子和网络安全应用的需求

最近面市的32位MCU具有包括闪存、ADC和其他功能在内的一整套集成外设,而且处理能力也得到了增强.这些新型的MCU为家电应用、消费电子产品和网络安全应用提供了高性能、低成本的解决方案.     

Low power high output impedance high bandwidth QFGMOS current mirror

Current mirror is a basic block of any mixed-signal circuit for example in an analog-to-digital converter. Its precise performance is the key requirement for analog circuits where offset is a measure issue. The key parameter which defines the performance of current mirror is its input/output impedance, input swing, and bandwidth. In this paper, a low power design of current mirror using quasi-floating gate MOS transistor is presented. The proposed current mirror boosts its output impedance in range of giga-ohm through use of regulated cascode structure followed by super-cascode. Another improvement is done in reduced input compliance voltage limits with the help of level shifter. The proposed current mirror operates well for input current range 0–700 $\mathrm{\mu }A$ with an input and output impedance of 160 $\Omega$ and 8.55 $\mathrm{G}\Omega$ respectively and high bandwidth of 4.05 $\mathrm{GHz}$. The total power consumption of the proposed current mirror is about 0.84 mW. The low power consumption with enhanced output impedance and bandwidth suits proposed current mirror for various high-speed analog designs. Performance of the presented current mirror circuit is verified using HSpice simulations on 0.18 $\mathrm{\mu }m$ mixed-mode twill-well technology at a supply voltage of ±0.5 V.