A novel architecture for improving slew rate in FinFET-based op-amps and OTAs

A new architecture for improvement of slew rate (SR) of an op-amp or an operational transconductance amplifier (OTA) in FinFET technology is proposed. The principle of operation of the proposed architecture is based on a set of additional current sources which are switched on, only when OTA should provide a high current, usually for charge or discharge of large load capacitor. Therefore, the power overhead is less compared to conventional high SR designs. The commonly used two-stage Miller-compensated op-amp, designed and optimized in sub 45 nm FinFET technology with 1 V single supply voltage, is used as an example for demonstration of the proposed method. For the same FinFET technology and with optimal design, it is shown that the slew rate of the op-amp is significantly improved. The slew rate is improved from 273 to $5590\mathrm{V}/\mathrm{\mu }\mathrm{s}$ for an input signal with a rise time of 100 ps. The other performance measures such as gain and phase margin remain unchanged with the additional circuitry used for slew rate enhancement.     

Low-voltage low-power CMOS RF low noise amplifier

In this paper, a 1 V, 2 GHz CMOS low-noise amplifier (LNA) was developed intended for use in the front-end receiver. The circuit is simulated in standard $0.25\mathrm{\mu }\mathrm{m}$ CMOS MOSIS. The LNA gain is 25.675 dB, noise figure (NF) is 4 dB, reverse isolation $(S_{12})$ is $-134.3\mathrm{dB}$, input return loss $(S_{11})$ is $-14.6\mathrm{dB}$, output return loss $(S_{22})$ is $-13.34\mathrm{dB}$, and the power consumption is 5.13 mA from a single 1 V power supply. One of the features of the proposed design is using a three-component cascode limitation, one of it is a transistor, to reduce the supply voltage.     

A current-mode analog multiplier/divider based on CCCDTA

A novel simple current-mode analog multiplier/divider, based on current-controlled current-differencing transconductance amplifier (CCCDTA), is presented. The proposed circuit employs only single CCCDTA without any external passive element requirement and it can work as multiplier and divider without changing its topology. In addition, the proposed circuit can work as gain-controllable current amplifier. The circuit performances are depicted through PSPICE simulations. The simulated results show that: for $\pm 1.5\mathrm{V}$ power supply, the total harmonic distortion is about 0.1%, the $-3\mathrm{dB}$ bandwidth is more than 26.94 MHz, maximum input range is about $100\mathrm{\mu }A$ and the output current is low sensitive to temperature variations.