SiC JBS二极管和SiC MOSFET的空间辐照效应及机理

基于第六代650 V 碳化硅结型肖特基二极管(SiC JBS Diode)和第三代900 V 碳化硅场效应晶体管(SiC MOSFET),开展SiC功率器件的单粒子效应、总剂量效应和位移损伤效应研究。20~80 MeV质子单粒子效应实验中,SiC功率器件发生单粒子烧毁(SEB)时伴随着波浪形脉冲电流的产生,辐照后SEB器件的击穿特性完全丧失。SiC功率器件发生SEB时的累积质子注量随偏置电压的增大而减小。利用计算机辅助设计工具(TCAD)开展SiC MOSFET的单粒子效应仿真,结果表明,重离子从源极入射器件时,具有更短的SEB发生时间和更低的SEB阈值电压。栅-源拐角和衬底-外延层交界处为SiC MOSFET的SEB敏感区域,强电场强度和高电流密度的同时存在导致敏感区域产生过高的晶格温度。SiC MOSFET在栅压偏置(U_GS=3 V,U_DS=0 V)下开展钴源总剂量效应实验,相比于漏压偏置(U_GS=0 V,U_DS=300 V)和零压偏置(U_GS=U_DS=0 V),出现更严重的电学性能退化。利用中带电压法分析发现,栅极偏置下氧化层内的垂直电场提升了陷阱电荷的生成率,加剧了阈值电压的退化。中子位移损伤会导致SiC JBS二极管的正向电流和反向电流减小。在漏极偏置下进行中子位移损伤效应实验,SiC MOSFET的电学性能退化最严重。该研究为空间用SiC器件的辐射效应机理及抗辐射加固研究提供了一定的参考和支撑。     

SiC junction-controlled transistors

The significant progress made over the past few years placed Silicon Carbide (SiC) power devices in a position to competitively challenge the existing standard Si solutions. This paper reviews the current trends regarding SiC junction-controlled devices and discusses the different approaches one may decide on when considering SiC junction field effect transistors (JFETs) for high power, high temperature applications.     

SiC材料与器件

介绍了碳化硅材料和器件的最新进展     

Thickness determination of low doped SiC epi-films on highly doped SiC substrates

The room temperature infrared reflectance of low doped SiC epi-films, both 4H and 6H polytypes, deposited by chemical vapor deposition on highly doped SiC substrates has been measured. The epi-film doping levels are in the 10¹⁵ cm⁻³ range while the substrate doping levels are in the 10¹⁸ to 10¹⁹ cm⁻³ range. Interference fringes from the epi-films are often observed in the frequency region below the reststrahl band in SiC (200–600 cm⁻¹) and they can be used to determine the thickness of these epi-films. The fringes arise due to the difference in free carrier concentration between the epi-film and substrate which causes differences in their frequency dependent dielectric functions. The epi-film thickness determinations were made by comparison of the measured infrared reflectance spectra to calculated spectra based on a frequency dependent dielectric function modeled with Lorentz oscillators using only bulk input parameters. The effects of film and substrate anisotropy and off normal incidence are included in the calculation.     

SiC microwave power technologies

Two SiC transistors that are investigated for microwave power applications are the 4H-SiC static induction transistor (SIT) and the 4H-SiC metal-semiconductor field-effect transistor (MESFET). Ultrahigh frequency 4H-SiC SITs have demonstrated record-breaking pulsed power per package (900 W) with excellent associated power-added efficiency (PAE) of 78%. S band 4H-SiC MESFETs have shown a record power-density of 5.6 W/mm and 36% PAE, as well as 80 W continuous-wave (CW) power (1.6 W/mm), with an associated PAE of 38%. X-band MESFET power density of 4.3 W/mm was obtained for exploratory CW devices. These performance gains are afforded by the advantageous material properties of silicon carbide. SiC SIT technology offers many military system advantages including lower cost, lower weight, higher power and high temperature of operation and higher efficiency transmitters with minimal cooling requirements. SiC RF MESFET's and circuits are candidates for use in efficient linear transmitters for commercial and military communications.     

今日SiC电子学

ＳｉＣ是近几年迅速发展的一种半导体材料,在微波功率器件、功率电子开关器件、高温工作器件等方面比Ｓｉ和ＧａＡｓ具有更大的优势。本文介绍了ＳｉＣ材料特性、材料制备及目前器件研制水平。     

SiC MOS interface characteristics

It is well known that SiC can be thermally oxidized to form SiO ₂ layers. And Si MOSFET IC's using thermally grown SiO₂ gate dielectrics are the predominant IC technology in the world today. However the SiC/SiO₂ interface has not been well characterized as was the case for Si MOS in the early 1960's. This paper presents data which for the first time characterizes the SiC/SiO₂ interface and explains one of the previously unexplained abnormalities observed in the characteristics of SiC MOSFET's     

SiC power modules emerging

Cree Inc has agreed with Advanced Power Technology, to purchase all of its SiC Zero Recovery Schottky Diode die to be packaged and sold as finished products under the APT brand name. APT intends to primarily address market segments not currently served by Cree, mainly by using alternative packaging and innovative engineering and use its expertise in high power semiconductor manufacturing to offer multi-die parallel discrete devices in a variety of packages, as well as in hermetic packages with and without military screening.This is a short news story only. Visit www.three-fives.com for the latest advanced semiconductor industry news.     

ICP etching of SiC

A number of different plasma chemistries, including NF₃/O₂, SF₆/O₂, SF₆/Ar, ICl, IBr, Cl₂/Ar, BCl₃/Ar and CH₄/H₂/Ar, have been investigated for dry etching of 6H and 3C–SiC in an inductively coupled plasma tool. Rates above 2000 Å cm⁻¹ are found with fluorine-based chemistries at high ion currents. Surprisingly, Cl₂-based etching does not provide high rates, even though the potential etch products (SiCl₄ and CCl₄) are volatile. Photoresist masks have poor selectivity over SiC in F₂-based plasmas under normal conditions, and ITO or Ni is preferred.     

A SiC backward diode

SiC backward diodes which operate between 77°K and 1000°K have been developed. Figures of merit (γ√R) of 19 300, 3960, and 15 at 12.5 MHz, 50 MHz and 8.8 GHz, respectively, have been measured with detector area on the order of 10^-5cm². These results are compatible with a prior analysis which predicted an upper frequency limit of between 0.1 and 1.0 GHz for SiC backward diodes.     

在半绝缘SiC衬底上制备的S波段2W碳化硅MESFET

介绍了用热壁反应炉在50mm SiC半绝缘衬底上制备的SiC MESFET外延材料.其沟道层厚度约为0.35μm,掺杂浓度约为1.7×1017cm-3.沟道和衬底之间的缓冲层为非有意掺杂的弱n型.欧姆接触用的帽层掺杂浓度约1019cm-3.器件制备采用了ICP刻蚀等技术.微波测试结果表明,1mm栅宽功率器件封装后在2GHz下输出功率达到了2W.     

SiC JFET与SiC MOSFET失效模型及其短路特性对比

建立了两种碳化硅（SiC）器件JFET和MOSFET的失效模型.失效模型是在传统的电路模型的基础上引入了额外附加的泄漏电流,其中,SiC JFET是在漏源极引入了泄漏电流,SiC MOSFET是在漏源极和栅极引入了泄漏电流;同时,为了体现温度和电场强度与失效的关系,用与温度和电场强度相关的沟道载流子迁移率代替了传统电路模型所采用的常数迁移率.有关文献的实验结果和半导体器件的计算机模拟（Technology Computer Aided Design,TCAD）验证了两种SiC器件失效模型的准确性.所建立的失效模型能够对比SiC JFET和SiC MOSFET的短路特性.     

n+多晶硅/n+SiC异质结欧姆接触

采用器件仿真软件ISE TCAD模拟了n+多晶硅/n+SiC异质结形成欧姆接触的新的SiC欧姆接触制造技术. 模拟结果表明n+多晶硅/n+SiC异质结接触可以形成良好的欧姆接触，具有工艺简单、性能优良的优点.     

n+多晶硅/n+ SiC异质结欧姆接触

采用器件仿真软件ISE TCAD模拟了n+多晶硅/n+ SiC异质结形成欧姆接触的新的SiC欧姆接触制造技术.模拟结果表明n+多晶硅/n+ SiC异质结接触可以形成良好的欧姆接触,具有工艺简单、性能优良的优点.     

n+多晶硅/n+ SiC异质结欧姆接触

采用器件仿真软件ISE TCAD模拟了n 多晶硅/n SiC异质结形成欧姆接触的新的SiC欧姆接触制造技术.模拟结果表明n 多晶硅/n SiC异质结接触可以形成良好的欧姆接触,具有工艺简单、性能优良的优点.     

Light and Strong SiC Networks

The directional freezing of microfiber suspensions is used to assemble highly porous (porosities ranging between 92% and 98%) SiC networks. These networks exhibit a unique hierarchical architecture in which thin layers with honeycomb‐like structure and internal strut length in the order of 1–10 μm in size are aligned with an interlayer spacing ranging between 15 and 50 μm. The resulting structures exhibit strengths (up to 3 MPa) and stiffness (up to 0.3 GPa) that are higher than aerogels of similar density and comparable to other ceramic microlattices fabricated by vapor deposition. Furthermore, this wet processing technique allows the fabrication of large‐size samples that are stable at high temperature, with acoustic impedance that can be manipulated over one order of magnitude (0.03–0.3 MRayl), electrically conductive and with very low thermal conductivity. The approach can be extended to other ceramic materials and opens new opportunities for the fabrication of ultralight structures with unique mechanical and functional properties in practical dimensions.     

碳化硅CMOS反相器的特性

建立了6 H- Si C CMOS反相器的电路结构和物理模型,并利用MEDICI软件对其特性进行了模拟.研究了Si C CMOS反相器的温度特性,结果表明,室温下沟道长度为1.5 μm的6 H- Si C CMOS反相器的阈值电压、高电平噪声容限和低电平噪声容限分别为1.6 5 7,3.15 6和1.4 70 V,且随着温度的升高而减小.