Finite-state Markov Model for Lognormal,Chi-square (Central), Chi-square (Non-central), and <Emphasis Type="Italic">K</Emphasis>-distributions

This paper formulates a finite-state Markov channel model to represent received signal-to-noise (SNR) ratios having lognormal, K-distribution, chi-square (central) and chi-square (non-central) distributions in a slow fading channel. The range of the SNRs is partitioned into a finite number of states following earlier works in literature. Performance measures like level crossing rates, steady-state probabilities, transition probabilities, and state-time durations are derived, and numerical results are plotted and discussed for the FSMC models for all the distributions.

Error Probability for <Emphasis Type="Italic">L</Emphasis>-branch Coherent BPSK Equal Gain Combiners over Generalized Rayleigh Fading Channels

In this paper, a closed-form expression for the probability of error in a coherent BPSK system over Generalized Rayleigh fading channels is derived. An L-branch equal gain combining diversity scheme is used. Theoretical results for the probability of error are plotted for various values of the number of degrees of freedom (n) and diversity order (L). A simulation is performed and the simulated results are found to match very well with the theoretical results.

Multiple Access <Emphasis Type="Italic">M</Emphasis>-ary Modulation UWB System Based on Code-Selected Direct Sequence Bipolar PAM

This work presents an M-ary multiple access code-selected direct sequence (DS) ultra wideband (UWB) communication system. A high data rate multiple access UWB system can be obtained by a code selection mechanism. In the proposed system, each user is assigned a DS code set with M/2 DS code sequence and a particular DS code sequence can be selected by the log₂ (M/2) bits from the DS code set. More importantly for this M-ary UWB communication system, with the increase of the modulation level M, it allows to reduce the required transmitter power maintaining the number of users, the data transmission rate and the multiple access performance. In this paper, we also introduce the detailed algorithm to compute the bit error rate (BER) over the AWGN channel and correlation receivers.

Overall Requirements for Global Information Multimedia Communication Village <Emphasis Type="Italic">10th Strategic Workshop</Emphasis>

The foundations for the definition of the network of the future should be based on a correct user and community characterizations to minimize the fragmentation of the experiences during the global interactions with information communication infrastructures. This paper describes some of the complex objectives and main challenges that telecommunication solution and services have to deal with in order to respect both specific requirements of global user interactions, habits and personalization, and framework requirements about green environments.

Efficient Mapping of CORDIC Algorithm for OFDM-Based WLAN

In an orthogonal frequency division multiplexing-based wireless local area network receiver there are three operations that can be performed by a unique coordinate rotation digital computer (CORDIC) processor since they are needed in different time instants. These are the rotation of a vector, the computation of the angle of a vector and the computation of the reciprocal. This paper proposes a common architecture of CORDIC algorithm suitable to implement the three operations with a reduced increase of the hardware cost with respect to a single operation CORDIC. The proposed architecture has been validated on field programmable gate-arrays devices and the results of the implementation show that area saving around 28% and throughput increment of 64% are obtained.

Reverse Breakdown Voltage Measurement for Power P<Superscript>+</Superscript>NN<Superscript>+</Superscript> Rectifier

The measurement of the reverse breakdown voltage for power rectifier is an important test. Two test methods for the reverse breakdown voltage measurement are employed in the industry, namely the forced voltage test (FVT) and the forced current test (FCT). In this work, we perform a systematic study to explain the different breakdown voltages obtained from the two test methods and the possible damage mechanisms to the device under test during FVT and FCT. The study shows that FVT has a much shorter test time while FCT is less destructive to the device under test.

Delay-dependent H ∞ control for 2-D discrete state delay systems in the second FM model

This paper is concerned with the problem of delay-dependent H _∞ control for two-dimensional (2-D) discrete state delay systems described by the second Fornasini and Marchesini (FM) state-space model. Based on a summation inequality, a sufficient condition to have a delay-dependent H _∞ noise attenuation for this 2-D system is given in terms of linear matrix inequalities (LMIs). A delay-dependent optimal state feedback H _∞ controller is obtained by solving an LMI optimization problem. Finally, a simulation example of thermal processes is given to illustrate the effectiveness of the proposed result.

Design and FPGA-Implementation of a High Performance Timing Recovery Loop for Broadband Communications

Timing recovery in communication systems with linear modulations is usually performed with a non-data-aided feedback loop based on a fractional interpolator timing corrector and the Gardner’s timing error detector. The contribution of this paper is twofold. First, some design rules are given to predict the behaviour of the loop if pipeline is used. Second, it is shown that pipelining can be used to reduce power consumption in a timing feedback loop. A timing recovery loop has been implemented in an FPGA device and power consumption measures indicates that by including 16 extra registers in the loop the power consumption decreases a 63% and the synchronizer can process up to 66.5 MSPS.

Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing

At-speed scan testing, based on ATPG and ATE, is indispensable to guarantee timing-related test quality in the DSM era. However, at-speed scan testing may incur yield loss due to excessive IR-drop caused by high test (shift & capture) switching activity. This paper discusses the mechanism of circuit malfunction due to IR-drop, and summarizes general approaches to reducing switching activity, by which highlights the problem of current solutions, i.e. only reducing switching activity for one capture while the widely used at-speed scan testing based on the launch-off-capture scheme uses two captures. This paper then proposes a novel X-filling method, called double-capture (DC) X-filling, for generating test vectors with low and balanced capture switching activity for two captures. Applicable to dynamic & static compaction in any ATPG system, DC X-filling can reduce IR-drop, and thus yield loss, without any circuit/clock modification, timing/circuit overhead, fault coverage loss, and additional design effort.

New Bit-Parallel Systolic Architectures for Computing Multiplication,Multiplicative Inversion and Division in GF(2<Superscript>m</Superscript>) Under Polynomial Basis and Normal Basis Representations

A new bit-parallel systolic multiplier over GF(2^m) under the polynomial basis and normal basis is proposed. This new circuit is constructed by m ² identical cells, each of which consists of one two-input AND gate, one three-input XOR gate and five 1-bit latches. Especially, the proposed architecture is without the basis conversion as compared to the well-known multipliers with the redundant representation. With this proposed multiplier, a parallel-in parallel-out systolic array has also been developed for computing inversion and division over GF(2^m). The proposed architectures are well suited to VLSI systems due to their regular interconnection pattern and modular structure.

Serial and Parallel FPGA-based Variable Block Size Motion Estimation Processors

H.264/AVC is the latest video coding standard adopting variable block size motion estimation (VBS-ME), quarter-pixel accuracy, motion vector prediction and multi-reference frames for motion estimation. These new features result in much higher computation requirements than previous coding standards. In this paper we propose a novel most significant bit (MSB) first bit-serial architecture for full-search block matching VBS-ME, and compare it with systolic implementations. Since the nature of MSB-first processing enables early termination of the sum of absolute difference (SAD) calculation, the average hardware performance can be enhanced. Five different designs, one and two dimensional systolic and tree implementations along with bit-serial, are compared in terms of performance, pixel memory bandwidth, occupied area and power consumption.

Robust Recursive <Emphasis Type="Italic">H</Emphasis><Subscript>∞</Subscript> DOA Estimation Using Spatial Forward Linear Predictor

This letter deals with robust direction of arrival (DOA) estimation based on the recursive H _∞ algorithm for the forward linear predictor. This recursive H _∞ criterion is different from traditional H ₂ estimation criterions which minimize the squared prediction error. The forward linear predictor with recursive H _∞ algorithm is a worst case optimization approach, which minimizes the total effect of the worst disturbances on the prediction error. Some computer simulation examples are provided for illustrating the effectiveness of the proposed method.

Cross-layer Routing Design in Cognitive Radio Networks by Colored Multigraph Model

In this paper, the cross-layer design routing in cognitive radio(CR) networks is studied. We propose a colored multigraph based model for the temporarily available spectrum bands, called spectrum holes in this paper. Based on this colored multigraph model, a polynomial time algorithm with complexity O(n ²) is also proposed to develop a routing and interface assignment, where n is the number of nodes in a CR network. Our algorithm optimizes the hop number of routing, meanwhile, the adjacent hop interference (AHI) is also optimized locally.

O<Superscript>3</Superscript>BPSK-based Linear Decorrelating Detector for Asynchronous DS/CDMA Systems over Frequency-Selective Rayleigh Fading Channels

In this paper, a convenient signaling scheme, called orthogonal on–off BPSK (O³BPSK), along with a simple one-shot linear decorrelating detector (LDD) and a whitening Rake bank, is proposed for near–far resistant detection in asynchronous DS/CDMA systems. Based on the maximum multi-path spreading delay, a minimum duration of “off” is suggested, during which the temporally adjacent bits (TABs) that contain multi-user interference (MUI) and inter-symbol interference (ISI) from different users at the receiver are decoupled. The O³BPSK signaling scheme is combined with the whitening Rake receiver to preserve multi-path diversity gain in multi-path fading CDMA channels. The scheme offers low complexity, no detection delay, near–far resistance, and compensation for fading channels.

P-cycle Protection in multi-domain optical networks

Providing resilient inter-domain connections in multi-domain optical GMPLS networks is a challenge. On the one hand, the integration of different GMPLS domains to run traffic engineering operations requires the development of a framework for inter-domain routing and control of connections, while keeping the internal structure and available resources of the domains undisclosed to the other operators. On the other hand, the definition of mechanisms to take advantage of such automatically switched inter-domain connectivity is still an open issue. This article focuses on the analysis of applicability of one of these mechanisms: P-cycle-based protection. The proposed solution is based on the decomposition of the multi-domain resilience problem into two sub-problems, namely, the higher level inter-domain protection and the lower level intra-domain protection. Building a P-cycle at the higher level is accomplished by certain tasks at the lower level, including straddling link connection, capacity allocation and path selection. In this article, we present several methods to realize inter-domain P-cycle protection at both levels and we evaluate their performance in terms of availability and spent resources. A discussion on a proposal of implementation of signalling based on extensions of existing protocols such as RSVP-TE and the PCE architecture illustrates the practical viability of the approach.

H ∞ filtering of 2-D discrete state-delayed systems

In this paper, we deal with delay-independent and delay-dependent H _∞ filtering problems for a class of two-dimensional (2-D) discrete time-invariant systems with state delays. The 2-D systems are described by local state-space (LSS) Fornasini–Marchesini (FM) second model. First, delay-dependent bounded real lemma is proposed through introducing free weighting matrices. Then the delay-independent and delay-dependent H _∞ filtering designs are developed to assure the stability and H _∞ performance γ of filtering error systems via LMIs’ feasibility. Furthermore, the minimum H _∞ norm bound γ can be obtained by solving linear convex optimization problems. Numerical examples demonstrate the effectiveness and advantages of our results.

Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores

The compiler is generally regarded as the most important software component that supports a processor design to achieve success. This paper describes our application of the open research compiler infrastructure to a novel VLIW DSP (known as the PAC DSP core) and the specific design of code generation for its register file architecture. The PAC DSP utilizes port-restricted, distributed, and partitioned register file structures in addition to a heterogeneous clustered data-path architecture to attain low power consumption and a smaller die. As part of an effort to overcome the new challenges of code generation for the PAC DSP, we have developed a new register allocation scheme and other retargeting optimization phases that allow the effective generation of high quality code. Our preliminary experimental results indicate that our developed compiler can efficiently utilize the features of the specific register file architectures in the PAC DSP. Our experiences in designing compiler support for the PAC VLIW DSP with irregular resource constraints may also be of interest to those involved in developing compilers for similar architectures.

Design of Power and Area Efficient Digital Down-converters for Broadband Communications Systems

This paper shows that when a digital receiver is designed utilizing two clock scopes, the digital down-converter can be designed to be efficient in terms of area and power consumption. The main design parameter that contributes to make the design efficient is the relationship between the transition band of the designed filter and its sampling frequency.

Comparison of <Emphasis Type="Italic">p</Emphasis>-cycles and <Emphasis Type="Italic">p</Emphasis>-trees in a unified mathematical framework

As high-speed networks grow in capacity, network protection becomes increasingly important. Recently, following interest in p-cycle protection, the related concept of p-trees has also been studied. In one line of work, a so-called “hierarchical tree” approach is studied and compared to p-cycles on some points. Some of the qualitative conclusions drawn, however, apply only to p-cycle designs consisting of a single Hamiltonian p-cycle. There are other confounding factors in the comparison between the two, such as the fact that, while the tree-based approach is not 100% restorable, p-cycles are. The tree and p-cycle networks are also designed by highly dissimilar methods. In addition, the claims regarding hierarchical trees seem to contradict earlier work, which found pre-planned trees to be significantly less capacity-efficient than p-cycles. These contradictory findings need to be resolved; a correct understanding of how these two architectures rank in terms of capacity efficiency is a basic issue of network science in this field. We therefore revisit the question in a definitive and novel way in which a unified optimal design framework compares minimum capacity, 100% restorable p-tree and p-cycle network designs. Results confirm the significantly higher capacity efficiency of p-cycles. Supporting discussion provides intuitive appreciation of why this is so, and the unified design framework contributes a further theoretical appreciation of how pre-planned trees and pre-connected cycles are related. In a novel further experiment we use the common optimal design model to study p-cycle/p-tree hybrid designs. This experiment answers the question “To what extent can a selection of trees compliment a cycle-based design, or vice-versa?” The results demonstrate the intrinsic merit of cycles over trees for pre-planned protection.     

Design of 100 μW Wireless Sensor Nodes for Biomedical Monitoring

Wireless sensor nodes span a wide range of applications. This paper focuses on the biomedical area, more specifically on healthcare monitoring applications. Power dissipation is the dominant design constraint in this domain. This paper shows the different steps to develop a digital signal processing architecture for a single channel electrocardiogram application, which is used as an application example. The target power consumption is 100 μW as that is the power energy scavengers can deliver. We follow a bottleneck-driven approach: first the algorithm is tuned to the target processor, then coarse grained clock-gating is applied, next the static as well as the dynamic dissipation of the digital processor is reduced by tuning the core to the target domain. The impact of each step is quantified. A solution of 11 μW is possible for both radio and DSP running the electrocardiogram algorithm.